The semiconductor industry is facing increasingly severe challenges. How should we respond?

If we compare transistors to food, we can refer to the methods of solving the food crisis to illustrate three ideas for dealing with chip challenges.

The first and most direct one is to continue to increase the output per unit area of staple foods, which corresponds to increasing the density of transistors in chips. This is called "More Moore."

The second is to expand other food types and increase the richness. This means that in addition to digital chips such as CPU and memory, we must also vigorously expand the uses of analog, radio frequency, power supply, display, flexible chips, etc., and use 3D chips to integrate various types of food. These functions are integrated together, which is called "More thanMoore".

The third, and most long-term, is to develop new food varieties, which corresponds to exploring new transistors other than MOS field effect transistors, such as carbon nanotube field effect transistors (CNTFET or CNFET for short), resistive switching memory (RRAM for short) , phase change random access memory (PCRAM for short), tunneling field effect transistor (TFET for short), etc. This path is called "Beyond Moore" (Beyond Moore).

01. "Continuing Moore"

The semiconductor industry continues to reduce the size of transistors and increase the density of transistors in chips, which is the main goal of "continuing Moore's" path.

When the process node advanced from 5 nanometers to 3 nanometers and 2 nanometers, FinFET encountered an old problem. The transistors could not be effectively turned off, and the leakage current soared, causing serious heating. Although FinFET has become a three-dimensional structure and can turn off the conductive channel through the three raised sides, it still cannot be completely turned off.

In 2003, researchers proposed a bolder "Nano-wire" structure. In this structure, the conductive channel of the transistor becomes a nanometer-thick "wire", completely surrounded by a ring-shaped "gate", just like a "hand" holding a rubber hose. Applying voltage to the "hand" turns off the transistor better and reduces leakage current.

Although this structure solves the problem of turning off the transistor, it also affects the amount of current that passes through the transistor after it is turned on: thin nanowires greatly hinder the current flow.

To this end, in 2006, researchers from the French Atomic Energy Commission's Laboratory of Electronics and Information Technology (CEA-Leti) proposed a nano-sheet structure. This type of transistor is also called GAAFET (see Figure 14-3). In this structure, the two sides of the transistor switch are no longer connected by thin "lines", but by thin and wide "pieces". This fully enclosed structure is more conducive to turning off the transistor, and multiple thin and wide "pieces" are more conducive to turning off the transistor. The film further improves the electrical conductivity. In 2017, IBM demonstrated this stacked nanosheet transistor. In May 2021, IBM used nanosheets to successfully break through the 2-nanometer technology node and integrate 50 billion transistors on a chip the size of a fingernail.

IRDS predicts that gate-around transistors will be used in technology nodes of 3nm, 2nm and below. Samsung is preparing to switch to gate transistors at the 3nm technology node, while TSMC is preparing to migrate to the 2nm technology node.

At the subsequent 1nm and 0.7nm technology nodes, the size of a single transistor will once again face challenges. IRDS predicts that the industry will then erect horizontally placed gate-around transistors to further reduce the "footprint." Going a step further, the industry may also stack gate-around transistors to create a 3D structure. Chips will continue to "grow" upward by stacking them, like layers of sky gardens, in order to continue to increase the number of transistors that can be accommodated per unit area.

Although a good transistor structure is designed, whether it can be manufactured is another matter.

The biggest bottleneck in manufacturing transistors remains the lithography machine. The minimum gate pitch that can be processed by an immersion lithography machine with a 193-nanometer light source is about 34 nanometers. You must know that 193 nanometer ultraviolet light (which becomes 134 nanometers after being refracted by water) itself cannot be used to process such a small size. It requires multiple exposures and multiple processing of different edges of the lines to achieve the required accuracy.

However, the smaller the processing size, the greater the number of masks required for multiple exposures of ultraviolet light. At the 7-nanometer technology node, dozens of layers of masks are required. The more masks, the more processing steps, and the more cost and time it takes. Wafers manufactured using the 10nm process are 32% more expensive than wafers manufactured using the 14nm process, and the 7nm technology node is 14% more expensive than 10nm. If the next-generation EUV lithography machine is not used at the 5-nanometer technology node, the number of steps required for lithography will reach more than 100 steps.

The light source wavelength of the EUV lithography machine (see Figure 14-4) is 13.5 nanometers, which is only 1/10 of the immersion lithography machine. It is the hope to solve this problem. However, the advent of EUV lithography machines has been delayed time and time again. As early as 1994, several companies in the semiconductor industry joined forces to launch the industrialization process of EUV lithography machines. Asmail delivered a photoresist scanning prototype in 2006, but then got stuck on the obstacle of a laser light source. EUV light with a wavelength of 13.5 nanometers was too difficult to generate.

Until 2011, California-based Cymer Semiconductor Equipment Company (Cymer) proposed a method to generate extreme ultraviolet lasers. Alberto Pirati, a lithography expert at ASML, commented: "When I first heard about this idea, I thought it was crazy." The idea is to heat metal tin at high temperatures Melting, extremely fine droplets are evenly sprayed into a cavity, and then a powerful beam of light is emitted from a high-power carbon dioxide laser to illuminate the droplets with 50,000 strobes per second and transform them into something resembling the sun. in the plasma, thereby stimulating EUV at 13.5 nm.

However, the efficiency of this method is extremely low. The laser requires an input power of 20 kilowatts (which can power 100 refrigerators), but can only obtain an output of 11 watts (equivalent to the power of an LED desk lamp), which is far less than that of photolithography. The remaining 99.945% of the energy required is 250 watts and is dissipated as heat.

As a last resort, Ximeng Semiconductor Equipment Company found a workaround: irradiate the drop particles with a low-power pilot laser to "flatten" them into a pancake shape to increase the light-receiving area, and then irradiate them with a high-power laser to Excite more EUV light. In 2013, the output light source power was increased to 55 watts, and in 2016 it reached 200 watts. In 2018 we finally reached the 250 watts required for actual work.

Although EUV light sources are available, new problems have emerged. EUV light cannot propagate through air because such short wavelength light is absorbed by the air. For this purpose, the light propagation path inside the machine and the area where the wafer processing table is located must be evacuated.

What's more troublesome is that glass lenses also absorb EUV light, so people have to abandon the lenses they have used for decades and use reflectors instead. However, ordinary mirrors also absorb EUV light. For this purpose, Asmail has invented a special mirror whose surface is alternately coated with thin layers of silicon and molybdenum, each only a few nanometers thick. Utilizing the Bragg effect of the different refractive indexes of the two materials, each interface can reflect a portion of the EUV light.

EUV light must pass through 12 reflectors before reaching the wafer stage, and each reflection loss is 30%. In the end, only about 1% of the light can illuminate the wafer. The original 250-watt light source only has 2 watts left when it shines on the wafer.

Such weak light requires the photoresist to be extremely sensitive, but highly sensitive photoresist will cause fluctuations in processing accuracy... Technical problems emerge in endlessly, and after one is solved, another one pops up.

After many delays, Asmail finally overcame unimaginable difficulties and manufactured the most sophisticated lithography machine in human history, each costing up to US$200 million.

In 2018, Asmail began delivering EUV lithography machines to customers. Each machine's components require four Boeing 747 aircraft to transport. Once it arrives at the fab, there will be hundreds of engineers ready to install and debug it. The lithography machine occupies about 80 square meters, of which the laser part occupies 20 square meters. The entire machine is like an iceberg, because a large number of pipes and cables are buried 10 meters underground, and then the part is exposed above the ground.

In 2020, after 17 years of research and development, EUV lithography machines finally began to be used for process manufacturing at the 5-nanometer node. It faces new challenges in the future. Technology nodes of 1 nm and below require higher resolutions. At this time, an EUV lithography machine with a high "numerical aperture" is needed, and the light source power required for the latter has to be doubled to 500 watts.

However, EUV lithography machines will soon reach their limits. IRDS predicts that the half-pitch will reach the limit of 8 nanometers in 2028 (in addition, although X-rays and electron beams have shorter wavelengths than EUV, X-rays require a large and expensive synchrotron radiation source, while electron beams Serial writing results in inefficiencies and is considered unsuitable for large-scale chip manufacturing). That would be the "cliff edge," and beyond that would be a world ruled by the uncertainty of quantum mechanics. When photolithography precision reaches its limit, transistor size cannot continue to be reduced.

The only possible way to continue to increase transistor density is to stack multiple layers of chips vertically, which is like turning a one-story bungalow into a high-rise building to increase transistor density. In fact, in the process before the EUV lithography machine, people have already started to use 3D stacking technology when manufacturing cost-sensitive memories. This way, there is no need to use the most advanced lithography machine and the cost can be well controlled. Currently, memories have been stacked in hundreds of layers.

In addition to the above difficulties, CPU performance improvement is also becoming slower and slower. In the 1990s, CPU performance could increase by 52% per year. In the first decade of the 21st century, it could only increase by 23% per year. From 2011 to 2015, this value dropped by nearly half, to only 12.5%. From 2015 to 2018, The year has almost stagnated at only 3.5%.

Moreover, the "memory wall" between the CPU and the memory is becoming increasingly difficult to overcome. The Von Neumann computer must first retrieve data from the memory and then send it to the CPU for calculation. However, after the CPU processing power has been significantly improved, the speed of the computer retrieving data from the memory has not increased proportionally, so a channel bottleneck has formed between the CPU and the memory.

The CPU quickly "digests" the data in its "belly", but new data cannot be "fed" from the memory for a long time, and the CPU has to be in a "hungry" state. It is estimated that the time it takes for the computer to transfer data from the memory is at least 10 times longer than the CPU processing time. The CPU can only waste precious time and resources waiting.

There are many reasons for the "high wall" between the CPU and memory. One of them is the distance between the CPU and memory. They are located on different chips, which can easily cause signal delays. In order to shorten this distance, people have proposed to package the CPU and memory in the same chip, place them on different layers, and then stack them into a three-dimensional chip. The layers are connected through silicon holes to shorten the signal transmission distance. However, even if the CPU and memory are in different parts of the same chip, the latency on the interconnect line is getting worse.

The way to completely solve the "memory wall" problem is to change the way the CPU retrieves data from the memory, no longer centering on the computing unit, but instead focusing on storage, and develop "in-memory computing" that integrates computing and storage. This new computer architecture has the potential to change the dominance of the "80-year-old" von Neumann computer architecture.

02. "Extended Moore"

As the obstacles to continuing Moore grew, people began to look for other solutions. In 2005, ITRS proposed the concept of "extended Moore". What this path pursues is not to reduce the size of a single transistor, but to increase the diversity of system functions and integrate and implement rich functions on one chip.

This path focuses not on digital chips such as CPUs and memories that require the most advanced processes, but on analog, power, sensing, and digital-to-analog hybrid chips that do not require the smallest transistors but can achieve a variety of application scenarios.

"Extended Moore" drives the development of technology based on top-level applications and needs. One of the biggest needs is the Internet of Things. In the past few decades, personal computers and mobile phones have become popular successively, but the number has reached saturation, and the number will increase by up to three times in the future. In the future, the number of IoT devices, including smart homes, health monitoring, self-driving cars, environmental monitoring, etc., will increase by three orders of magnitude, forming a ubiquitous IoT world.

For example, self-driving cars require laser ranging radar, ultrasonic sensors, accelerometers and other sensors; the medical field requires wearable physiological signal monitoring equipment, as well as implanted sensors and current stimulation chips to suppress epileptic seizures; The field of environmental monitoring requires sensor chips that can detect various pollutants such as carbon dioxide and sulfide. These sensors need to be integrated with CPU, memory, etc. to achieve rich functions.

In addition, we also need efficient power supplies to achieve extremely low power consumption to meet the requirements of portable or mobile devices. We also need to use high signal-to-noise ratio sensors and analog circuits to sense or collect weak physiological signals, concentrations of dangerous gases, etc. We also need wireless radio frequency circuits that meet various frequency bands to achieve more diverse wireless connections.

Another area where there is a need to "expand Moore" is the energy field. Compared with silicon, semiconductor materials such as gallium nitride and silicon carbide have better performance. Power devices made of them can provide higher switching frequencies at the same withstand voltage, or switch at the same withstand voltage. There are lower conduction and switching losses at frequency.

In addition, people will also have a huge demand for energy harvesting technology, because many sensors are placed in open-air environments without mains power supply, and it is inconvenient to replace batteries. The energy collection methods can be mechanical vibration, hot and cold temperature difference or radio waves, light, etc., which will greatly extend the working time of the chip.

Finally, flexible electronics will play a role in fabric-based wearables, foldable screens, thin-film solar cells, and more. In the future, a considerable number of flexible electronic devices will be manufactured by printing on flexible substrates, but this requires the industry to make further breakthroughs in organic materials and carbon-based materials.

Starting in 2017, a technology called chiplet has attracted the interest of the industry, especially AMD. In the past, people tried to integrate different circuit modules onto one chip to reduce costs. But it was found that the larger the chip area processed, the lower the chip yield (the ratio of good-performing bare chips on the wafer), which in turn drove up costs. On the contrary, breaking large chips into small chips can improve yield and reduce costs.

As a result, a reverse trend emerged: dismantling large chips into smaller individual chips, manufacturing them separately, and then combining them together through packaging technology (see Figure 14-5). It's a bit like making small pieces of Lego and then putting them together into a larger whole. For example, if a chip with an area of 360 square millimeters is split into four small chips and made separately, its yield will be more than doubled. Under this trend, there will be more and more cores in CPUs in the future. There are 8 small chips in an AMD EPYC processor (EPYC for short), and each chip has 8 cores, for a total of up to 64 cores.

Small chip technology adds a degree of freedom to the chip system, that is, each small chip can be freely manufactured using the most cost-effective process. CPU and memory use advanced processes to increase computing power, while simulation and radio frequency use relatively low-cost processes. Low-cost mature technology to reduce overall costs.

When Kilby and Noyce invented the integrated circuit from 1958 to 1959, they solved the problems of integration and interconnection respectively. Now more than 60 years later, we are still on the road to pursuing better integration and interconnection. The integration method has moved from two-dimensional to three-dimensional, from single chip to multi-chip, from single circuit interconnection to the integration of digital, analog, radio frequency, sensor and other circuits, and from silicon integration to silicon, carbon, germanium and other elements. joint integration, moving from planar interconnection to three-dimensional interconnection.

03. “Beyond Moore”

The computing needs of new technologies such as big data, the Internet of Things, artificial intelligence and supercomputing have put forward higher requirements for chip performance and energy efficiency, so there is a third way: "Beyond Moore", also called "Beyond CMOS". That is, looking for better possibilities outside of mainstream CMOS technology.

Leakage currents in silicon transistors have long been a concern for scientists. For this reason, people invented TFET (its structure is shown in Figure 14-6). It uses the quantum tunneling effect between the conduction band and the valence band to control the opening and closing of the transistor, making the leakage current smaller and the conduction current larger, breaking through the Maxwell-Boltzmann statistical limitations of traditional transistors, making The subthreshold swing is below the lower limit of 60 mV/dec. However, the source and drain of TFET are no longer P-type semiconductors or N-type semiconductors like MOS field effect transistors. Instead, one side is a P-type semiconductor and the other side is an N-type semiconductor. This has a great impact on device manufacturing and application. presented new challenges.

Although silicon material is suitable for mass production, has abundant storage, and has a naturally stable insulating oxide layer, it also has shortcomings that are difficult to overcome: low electron mobility, resulting in low switching speed; average heat dissipation characteristics, limiting the working frequency of the chip . These problems make the road to "continuing Moore" difficult.

Carbon materials, on the other hand, have advantages in mobility, small size, and heat dissipation properties. In the laboratory, researchers have used carbon nanotubes to make CNTFETs (see Figure 14-7). The structure is similar to silicon MOS field effect transistors, except that the middle conductive channel has been replaced with better mobility and better heat dissipation. , smaller carbon nanotubes. Currently, the challenges of large-scale preparation are still being addressed.

Whether it is BJT or MOS field effect transistor and other devices, electrons are used as the medium for information processing, and the innovative idea is to use faster photons. Photons have no heat dissipation problem and are not affected by electronic noise. Moreover, the delay of optical signals is small, and the communication bandwidth is much higher than that of electrical signals.

In addition, various optical processing devices (optical waveguides, optical filters, optical connectors, etc.) can be made using silicon materials, and they can be easily integrated into CMOS chips, thus greatly reducing costs. It is starting to become possible to manufacture optical interconnect processors. However, silicon photonics still needs to break through some technical bottlenecks before it can enter practical applications.

In 1970, Professor Leon Chua of the University of California, Berkeley, discovered that there were three basic components: resistors, which are responsible for relating voltage and current; capacitors, which are responsible for relating voltage and charge; and inductors, which are responsible for relating current and magnetic flux. But can charge and magnetic flux be directly related? Cai Shaotang proposed that there may be a fourth basic component that can directly relate charge and magnetic flux, which he named memristor (see Figure 14-8). In 2008, a team led by Williams at HP Labs made a single-device structure of memristor, consisting only of metal at both ends and an oxide in the middle.

Memristor has a resistance memory effect, which can maintain the resistance value after power off, and can change the resistance value under the stimulation of pulse signals, just like the synapses in the brain change the connection strength under the stimulation of neuron pulses, and can be used as artificial electronic synapses. Simulate chemical synapses in the brain to achieve learning and memory functions. The size of memristors can reach nanometer scale, but there is still a lot of room for improvement in terms of production yield and device consistency.

In addition, people have also carried out research on spin field effect transistors (Spin-FET for short), PCRAM, RRAM, magnetoresistive random access memory (MRAM for short), flexible thin film transistors (FTFT for short), etc., but Due to the low cost and large output of traditional devices, the advantages of these new devices cannot yet be reflected and cannot replace existing devices in the short term.

However, "danger" hides "opportunity". The end of the road to transistor shrinkage may be good news, because most of the industry's funds and manpower have previously been invested in related research on silicon MOS field-effect transistor devices to maintain its progress at the speed predicted by Moore's Law. Now, the end of MOS field effect transistor size reduction will make way for the development of non-MOS field effect transistor devices.

In the EDA field of chip design, as digital, analog, radio frequency and other circuits in the chip are integrated into one system, electromagnetic interference will become more complex, heat dissipation issues and performance degradation need to be dealt with more carefully, and the interfaces between different circuits will also become more complicated. In recent years, artificial intelligence has begun to be used to solve chip wiring problems to find optimal solutions.

At the application level, in order to meet the computing needs in different scenarios, people are researching chip technologies that integrate high-bandwidth memory (HBM), in-memory computing, near-memory computing, neuromorphic computing, approximate computing and integrated sensing, storage and computing.

Will these ideas be realized in the future? We don't know for sure yet, but they will definitely appear in the future in a way that we have never seen, heard, or even imagined, shattering the conclusions we once believed in. Perhaps the answer here is to borrow a quote from computer scientist Alan Kay: “The best way to predict the future is to invent it.”

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