Dan Kochpatcharin, director of TSMC's Ecosystem and Alliance Management Division, recently wrote that we are on the brink of the artificial intelligence era, and demand for high-performance AI chips in data centers is surging. In fact, it can be said that now is the best time for the semiconductor industry to grow as our innovations are unlocking tremendous opportunities in the field of artificial intelligence.

As next-generation AI chip designs become larger and more complex, and time frames to market become increasingly compressed, the need for more powerful, more energy-efficient advanced chips is growing. At the TSMC 2024 North American Open Innovation Platform® (OIP) Ecosystem Forum, we met with design partners and customers to explore how TSMC and the broader semiconductor industry can collaborate to address these challenges and seize emerging opportunities.

TSMC is advancing the 3D IC design ecosystem to promote system-level innovation by strengthening collaboration with partners, customers and foundries. Working with our OIP ecosystem partners, we are leveraging artificial intelligence and machine learning to significantly improve 3D IC design productivity and optimize design power, performance, area (PPA) and quality of results (QoR).

As a proud member of the 3Dblox Council, we are working with other committee members to drive the next evolution of the 3Dblox standard, significantly improving 3D IC design efficiency and moving the industry forward. Together with our OIP partners, we address the multi-physics challenges inherent in 3D IC architecture, helping our mutual customers achieve accurate and optimized designs on the latest TSMC 3DFabric technology.

01 Views from our Our partners

"Our collaboration with TSMC to deliver advanced silicon solutions for AWS-designed Nitro, Graviton, Trainium, and Inferentia chips has enabled us to push the boundaries of advanced process and packaging technologies to provide our customers with the best price/performance for virtually any workload running on AWS." – said Gary Szilagyi, Vice President, AWS Annapurna Labs.

"Broadcom successfully launched the industry's first Face-to-Face 3D SoIC in September 2024. The device uses TSMC's 5nm process, 3D chip stacking, and CoWoS packaging technology to integrate 9 chips and 6 HBM stacks in one large package. This paves the way for the high volume 3D-SoIC production ramp expected in 2025. Broadcom's continued use of 3Dblox is a welcome advancement for the interoperability of EDA tools in the 3D IC design flow." – said Greg Dix, Vice President, R&D and Engineering, ASIC Products Division, Broadcom.

"TSMC's 2nm technology delivers superior performance and power efficiency, coupled with its 3DFabric, driving Socionext's 3D IC innovations to deliver scalable solutions for a variety of applications such as data centers, 5G/6G infrastructure, and edge computing. TSMC's technology and its comprehensive ecosystem help Socionext significantly reduce the time to market to bring competitive products. These innovations are critical to solidifying Socionext's leadership in the global market as a supplier of fully customized and optimized solutions for fields such as automotive, data centers, and networking that require the most advanced technologies." - said Hisato Yoshida, Vice President and Head of Global Development Group at Socionext. With the rapid adoption of AI, the industry is pushing the boundaries of advanced process and 3D IC technologies to meet the unprecedented demand for advanced silicon solutions capable of handling massive data sets and computations. TSMC and our OIP ecosystem partners are at the forefront of this paradigm shift, working together to provide advanced EDA and IP solutions leveraging TSMC's most advanced process and 3DFabric technologies to accelerate the advancement of 3D IC design and drive AI innovation.

We work with our OIP partners to certify their industry-leading digital and custom full design flows using the latest advanced 3nm and 2nm technologies to ensure successful tapeouts for our customers. Our latest collaboration also includes TSMC certified design platforms supporting TSMC 3DFabric technology, which incorporates TSMC-SoIC (System on Integrated Chip) and CoWoS, including the latest System on Wafer (TSMC-So) packaging.

Continuing our tradition of Design Technology Co-Optimization (DTCO), we work with long-term partners to optimize power, performance, and area (PPA) for the latest TSMC technologies such as N3 FinFLEX, N2 NanoFLEX, and the latest TSMC A16, as well as innovative backside power solutions to power future AI innovations.

As the demand for compute in AI applications continues to grow, semiconductor technology must keep pace. We work with key design ecosystem partners to develop AI-based design automation to deliver industry-leading productivity and quality of results (QoR). In fact, our EDA partners have already achieved significant improvements in timing, power, and productivity using AI/ML in semiconductor design.

We are working with partners to apply generative AI to improve design efficiency, using large language models (LLMs) for workflows, running assistant flow scripts and register transfer level (RTL) design and debugging, as well as knowledge assistant tools and using flow queries. This approach helps significantly improve design efficiency and accelerate the process from idea to successful design.

We are also working with major electronic design automation (EDA) partners to apply AI to design work, including digital design metal scheme optimization, cell library and EDA setup optimization, analog design migration, analog circuit optimization and 3D IC design space exploration. AI-driven solutions simplify the floorplanning process to optimize thermal, signal and power integrity to maximize system performance and QoR.

These methods are just a few examples of our close collaboration with OIP partners to achieve the goal of migrating future AI chip designs from analog design to 3D IC design space exploration.

The 3Dblox open standard, launched in 2022, provides a way for EDA vendors to model the basic physical stackup and logical connectivity information of 3D IC designs in a single format. 3Dblox simplifies 3D IC design by providing a comprehensive view of physical and logical connections and enhancing cross-tool interoperability.

Since its inception, the 3Dblox standard has undergone multiple updates, each evolution making it easier to use for partners and their customers. In 2022, 3Dblox implemented a modular approach to represent all 3D IC architectures. Last year, 3Dblox enhancements focused on prototyping feasibility for early architectural exploration. Now, the latest version of 3Dblox has been further developed to effectively handle large 3D IC designs with early planning capabilities.

02 Latest 3Dblox

AI-based global resource optimization: By leveraging the power of EDA AI engines to fully explore the electrical and physical design space, complex 3D IC designs can be efficiently and successfully partitioned into separate 2D IC designs to maximize productivity.

Multi-physics analysis convergence: Due to thermal coupling, 3D IC systems have stronger dependencies between timing, power, electromigration/IR drop (EMIR), and thermal analysis. This new feature greatly reduces the setup effort by seamlessly integrating multiple analysis engines under the same database, thereby simplifying data transfer and precise convergence control.

Early floorplanning design rule checking (DRC): Rotation, flipping, and projection of chips is a complex process, which complicates DRC in a 3D environment. This new feature identifies critical 3D floorplanning rules necessary for correct floorplanning, effectively separating planning from final implementation checks. Automatic alignment mark insertion: As 3D integration sizes increase, more alignment marks are required for process control. TSMC has achieved a fully automated, one-by-one correction process, eliminating the complexity of calculating the coordinates of each alignment mark by rotating, flipping, projecting, or optically shrinking the die. This new approach greatly simplifies the alignment mark insertion process.

3Dblox Universal Constraints for Early Chip-Package Co-Design: The industry lacks a common protocol for the early stages of chip-package co-design. The 3Dblox Universal Constraint Format bridges this gap by providing a formal definition of the required constraints to facilitate precise communication between teams and ensure rapid convergence of packaging and integration rules.

In addition to these new developments, the 3Dblox committee also announced plans to publicly release the 3Dblox standard through IEEE, the world's largest technical professional organization, to further drive innovation in the 3D IC design ecosystem and improve interoperability of EDA tools. Known as IEEE 3537-3Dblox, the standard will receive more support and resources from industry experts, while making it easy for more partners, customers, and foundries to leverage 3Dblox to break new ground in AI technology and other areas.

03 COWOS's production capacity has made a great leap forward

Morgan Stanley reportedly estimates that TSMC's original plan to increase CoWoS packaging capacity to 80,000 wafers per month in 2026 has progressed faster than expected, so the company can achieve this goal in 2025, and TSMC's acquisition of a NT$17 billion plant in Taiwan in August has greatly helped this timeline.

The analyst is also optimistic about TSMC's current leading 3-nanometer chip manufacturing process. He believes that 3-nanometer capacity can grow from 90,000 wafers per month in 2024 to 120,000 wafers per month in 2025. As with packaging, demand from the artificial intelligence industry is expected to help capacity increase.

For the latest AI chips, packaging and manufacturing must go hand in hand, as the latter ensures performance superiority and power efficiency; the former is responsible for assembling the chip into a form that can be used in the final product.

Intel's transfer of some chip manufacturing needs to TSMC is also expected to drive demand for TSMC's 3nm process technology. While this assumption is reflected in the analysts' model, the bank cannot confirm whether this is the case in reality. Chip demand for the iPhone is expected to play a role in the capacity increase, especially since Apple's 2025 iPhone should continue to use the 3nm node and use the advanced N3P variant.

TSMC is also expected to increase production capacity at its latest manufacturing technology, the 2nm node. Although Apple's orders will not materialize next year, Morgan Stanley believes that 2nm capacity can be expanded from 10,000 wafers per month in 2024 to 50,000 wafers per month in 2025. This number will further grow to 80,000 wafers per month in 2026 as iPhone production increases in 2026. By 2026, 3nm capacity is expected to reach 140,000 wafers per month, including 20,000 wafers at TSMC's U.S. manufacturing facilities.

The Morgan Stanley analyst also raised his forecast for capital expenditures through 2025. He sees capital expenditures growing 8.5% in 2025, from $35 billion this year to $38 billion next year. Geopolitical tensions coupled with surging demand for artificial intelligence require TSMC to expand its manufacturing capabilities and shift its production base away from Taiwan. These plans include opening new plants in the United States and Japan, and media reports say TSMC is discussing building chip manufacturing plants in water-scarce regions of the Middle East.

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