The semiconductor industry is constantly evolving, and while evolution is a good thing, it also means that some mature technologies will inevitably decline. As industry insiders know, many foundries have issued last-buy notices for 600 nm ASICs as they move to more efficient, smaller geometry nodes.

This will force companies in the automotive, aerospace, defense, telecommunications, and consumer electronics industries to rethink their semiconductor designs. However, as we will discuss, this is not necessarily bad news.

01 Review of the Development of Semiconductors

There have been many important milestones in the development of semiconductor technology. The development of the 10 µm process in 1971 led to the Intel 4004, the world's first commercially produced microprocessor with 2,300 transistors.

After this breakthrough, the semiconductor industry moved at a rapid pace, with the introduction of the 6 µm process in 1974 and the 3 µm process in 1977. Each iteration was an improvement over the last. By this time, Moore's Law had been established. It predicts that chip density will double roughly every two years as semiconductor technology advances exponentially.

By the early 1980s, transistors had shrunk to 1 micron, and companies were routinely packing more than 100,000 transistors on a single chip. By the 1990s, transistor counts had exceeded 1 million, and the 600-nanometer process debuted. According to relevant information, the 600 nm process was commercialized by leading semiconductor companies such as Mitsubishi Electric, Toshiba, NEC, Intel, and IBM around 1990 to 1995.

At the same time as this process was unveiled, the term "sub-micron" had become a reality, and the 600 nm process played a core role. This era introduced CMOS technology, which could integrate up to 4 million bits of SRAM and 16 million bits of DRAM, which was a major leap at the time.

According to incomplete statistics, Mitsubishi Electric, Toshiba, and NEC launched 16 Mbit DRAM memory chips manufactured using the 600 nm process in 1989; NEC launched 16 Mbit EPROM memory chips manufactured using the process in 1990; Mitsubishi launched 16 Mbit flash memory chips manufactured using the process in 1991; the Intel 80486DX4 CPU launched in 1994 was manufactured using the process; the IBM/Motorola PowerPC 601 was the first PowerPC chip produced using the 600 nm process; the 75 MHz, 90 MHz, and 100 MHz Intel Pentium CPUs were also manufactured using this process.

It is worth noting that during this period, Intel transitioned from the 486 processor using 600 nm technology to the first generation of Pentium processors using the more advanced 350 nm process.

In the 600 nm era, 8-inch (200 mm) wafers became the industry standard and 5 V logic levels were widely used. This period also saw the development of various process variants, including BiCMOS and BCD technologies, which enabled mixed-signal applications with both analog and digital signals. These innovations allowed products developed based on the 600 nm process to continue to be produced for many years, for use in everything from consumer electronics to industrial equipment.

Despite the impressive performance of the 600 nm process, the continued progress of Moore's Law pushed the industry toward smaller geometries, higher logic densities, and larger wafers. The introduction of 12-inch (300 mm) wafers and the shift to lower logic voltages such as 3.3 V marked the beginning of a new chapter.

Wafer foundries initially maintained dual production lines for 200 mm and 300 mm wafers, but advances in technologies such as copper metallization and shallow trench isolation (STI) made it increasingly challenging to maintain both lines profitably.

This evolution has led to the current situation. Many foundries are issuing last-buy notices on their classic 600 nm processes, prompting manufacturers to consider migrating to newer technologies.

02 Why abandon 600nm now?

As semiconductor processes advance from 600 nanometers to smaller geometries, materials used in older technologies are increasingly difficult to source and often no longer comply with current environmental and safety regulations. Maintaining equipment for these outdated processes has also become increasingly expensive, making it impossible for foundries to continue producing.

The significant advantages of the new process cannot be ignored. Processes such as 130 nm and 180 nm enable higher logic density, higher power efficiency and higher reliability, with features such as copper metallization and shallow trench isolation (STI). The transition to 12-inch (300 mm) wafers further solidifies these new processes as industry standards, delivering better performance and cost-effectiveness for modern applications.

As a result, many wafer factories have issued final purchase notices for ASICs of this process.

While the initial reaction to a last-minute purchase notice may be concerns about the cost and complexity of migrating your design, this should be viewed as an opportunity rather than a business-stagnant problem to overcome. Higher performance, lower power consumption and enhanced functionality become easier to achieve.

Foundries such as GlobalFoundries (GF), Taiwan Semiconductor Manufacturing Company (TSMC), XFAB and SK keyfoundry offer a wide range of options to facilitate migration from 600 nm. This ensures a stable supply chain while opening the way for product improvements and innovation.

The shift to modern processes is critical for industries such as automotive manufacturing, where industry standards are strictly enforced and a reliable supply chain is essential for production.

Let's start with the benefits. There are many advantages to migrating designs from 600 nm or 350 nm to more advanced processes such as 180 nm or 130 nm:

1) New technologies provide higher logic density, allowing more functionality to be implemented in the same silicon area. 

2)More complex and powerful circuits can be integrated, enhancing overall product functionality. 

3)Advanced nodes can support higher clock frequencies or lower power consumption, depending on design requirements. 

4)Copper BEOL metallization and up to eight metal layers improve resilience to electromigration and provide better performance for high-speed signals. 

5)Shallow trench isolation (STI) technology increases density and reduces the risk of "latch-up," a common failure point in older processes.

Comparison of characteristics of four silicon transistor nodes

However, compatibility with existing designs should be a major consideration. Many newer processes offer dual gate oxide options, providing the benefits of more modern technology while maintaining compatibility with older 5 VI/O standards. This ensures that designs can be updated with minimal changes to the original specifications.

In addition, the 130 nm BCD node is now a very mature technology, offering more process options, including transistors of different high voltage levels, non-volatile memory (OTP, Flash), MIM capacitors, Zener or Schottky diodes, etc. This facilitates the integration of complex analog/RF functions into more competitive system-on-chip solutions. Higher levels of integration provide options for fine-tuning on-chip analog functions and calibrating external sensors, providing system-level cost benefits.

The smaller feature size of 130 nm allows the integration of Arm Cortex-M class processors (or similar RISC-V) with little additional silicon cost. In fact, the required CPU performance and memory requirements will become the main factors in the feasibility of integration. Low-end CPUs only require a few square millimeters of silicon area. Likewise, 64 or 128 Kb of SRAM can be integrated in a cost-effective manner.

The availability of a large number of silicon-proven third-party IP, both analog and digital, simplifies the integration of additional functionality that was simply not possible in 600 nm processes. In addition, improved lithography techniques for newer 12-inch wafers reduce defectivity and enable better device matching, thereby increasing manufacturing yields.

03 It's not a bad thing

Migrating a 600 nm or 350 nm CMOS product to a 130 nm process involves several key steps and considerations, often starting with a thorough evaluation of whether the new design is pin-compatible with the old design or whether it should include new features.

This decision will significantly impact the amount of engineering effort required. For example, a complete redesign may be necessary due to the age and potential obsolescence of the original design database. This will involve planning and technology selection, design, simulation and validation.

It's also worth noting that, depending on the complexity, the design work can take several months. Then, it takes another three months or more for manufacturing and additional time for verification and qualification. In short, the presence of a legacy design database does not guarantee automatic migration of designs.

However, migrating to newer process technologies such as 130 nm ensures continuity and provides opportunities for enhancement and modernization. For example, automotive safety standards such as ISO 26262 (which did not exist in the 600 nm era) can be seamlessly integrated into new designs without significantly increasing silicon area.

New technologies also enable higher levels of integration, allowing for additional features such as integrated sensors and enhanced communication interfaces. This can significantly change the value and usage of various products. Of course, there are benefits to leveraging modern supply chains. Most 300mm fabs already offer certain certifications, which facilitates a smoother production process. This is particularly beneficial for industries that require long-term supply commitments, such as aerospace and automotive.

In that sense, it's a win-win! Redesigning older aerospace components into newer technology can reduce costs and improve performance while meeting strict qualification requirements. This can transform older products into more competitive and future-proof solutions, opening up new market opportunities and extending their life cycles.

So the last purchase notification isn't scary; it's just an innovation. With the right mindset and some careful planning, it will raise the bar for everyone.

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