Article Outline 

DRAM Overview 

 · Dynamic Random Access Memory 

 · Development Bottleneck 3D DRAM

3D DRAM

· 3D DRAM

· DRAM Structure Still Needs Improvement 

DRAM Technology Development Prospects

· DRAM Commercial Market

· 3D DRAM Technical Challenges

· 3D DRAM Layout of Leading Companies

DRAM Overview

1.1 Dynamic Random Access Memory

The basic working principle of dynamic random access memory (DRAM) is to store one bit of information (i.e. 0 or 1) through transistors and capacitors in the storage unit. In DRAM, the basic storage unit structure is called 1T1C, where 1T represents a transistor and 1C represents a capacitor. The transistor acts as a switch here, controlling whether the capacitor allows charge to flow in or out. The capacitor is responsible for the actual charge storage. When the capacitor is fully charged, it means that a 1 is stored; conversely, when the capacitor is discharged, it means that a 0 is stored.

Because the charge of a capacitor leaks away over time, DRAM needs to be refreshed periodically to maintain data stability. The refresh mechanism involves periodically recharging the capacitor to ensure that it accurately reflects the stored information. This constant refreshing of the charge maintains data integrity, but it also consumes a certain amount of power.

DRAM is a volatile memory, which means that the data stored in it will disappear quickly after the power is turned off. Therefore, DRAM is mainly used in scenarios that require high-speed access and transmission of data, especially those applications that require frequent reading and writing. Compared with other storage technologies, DRAM has the advantages of high speed, large capacity and relatively low cost, which makes it a key component in modern electronic devices.

In practical applications, DRAM is widely used in personal computers, servers, smart phones, tablets and other devices, and is mainly responsible for storing temporary data. These data include the core parts of the operating system, running application data, and users' real-time operation data. Due to the high-speed characteristics of DRAM, it can efficiently handle multi-threaded tasks, real-time computing, and large-scale data operations that require fast data access. The development of DRAM has been accompanied by the continuous advancement of semiconductor technology. Its storage density and speed are gradually increasing, while the cost remains at a relatively low level. This has led to the continuous expansion of the application scope of DRAM in the computer field, and it has become an important foundation for supporting the performance of modern computing devices.

1.2 Development bottleneck

As the advancement of Moore's Law gradually slows down, DRAM technology is facing an increasingly severe bottleneck period. In the past few decades, driven by Moore's Law, the semiconductor industry has experienced rapid development, the size of transistors has continued to shrink, and the integration on chips has become higher and higher, bringing higher memory capacity. However, as the size of transistors approaches the physical limit, the progress of DRAM technology has begun to slow down, and the challenges have become more prominent.

From a technical point of view, the reduction in transistor size means that more transistors can be integrated into a chip, which directly increases the memory capacity of the chip. At present, the manufacturing process of DRAM chips has broken through to the 10nm level, which is an important technical milestone, indicating that the storage density has reached an unprecedented level. However, although 10nm technology has made significant progress, it is not the ultimate limit of DRAM development. Future technology nodes may continue to advance to smaller sizes, but this process is accompanied by great technical challenges.

As DRAM process nodes continue to shrink, challenges in multiple aspects are becoming more and more obvious. The first is the problem of process integrity. As the size decreases, the tolerance for errors in the manufacturing process becomes lower and lower, and any tiny defects may cause transistor failure and affect the performance of the entire chip. The second is the cost issue. Manufacturing smaller transistors requires more complex processes and more expensive equipment, which significantly increases production costs. Especially in the context of the current global semiconductor shortage, the cost issue is particularly prominent.

The capacitor leakage problem has also become more serious as the size decreases. DRAM relies on capacitors to store charge, but when capacitors become smaller, the risk of charge leakage increases, resulting in reduced data reliability. To solve this problem, engineers need to develop new materials and design methods to reduce leakage rates and improve data retention capabilities. Another major challenge is the interference problem. On highly integrated chips, electric and magnetic field interference between different storage cells becomes more frequent, which can cause data errors or damage. To deal with this problem, more complex error correction mechanisms and anti-interference designs are required, which further increases the difficulty of DRAM development.

As DRAM technology line widths enter the 10nm range, physical limitations such as capacitor leakage and interference become more prominent. These problems not only stem from the reduction in transistor size, but are also closely related to a series of physical limits, such as the enhancement of quantum tunneling effects, the increase of leakage current, and the decrease of thermal stability. These physical effects become more and more obvious in ultra-small transistors, resulting in a significant reduction in the charge retention capacity in DRAM memory cells, which in turn affects the reliability of data. In addition, as the dielectric thickness decreases, the value of the capacitor also decreases, which further exacerbates the increase in leakage current and shortens the data retention time.

In addition to physical limits, the challenges of material science are becoming increasingly severe. For example, the performance of traditional silicon-based materials degrades at ultra-small sizes, and the reduction in the thickness of dielectric materials leads to a decrease in the performance of capacitors. In order to meet these challenges, the precision control requirements of the manufacturing process have become more stringent, and any slight process deviation may cause the failure of the memory cell. Therefore, continuing to use the two-dimensional (2D) method to reduce the size of devices, especially in the so-called 4F² scaling (i.e., increasing storage density by reducing the area occupied by transistors), has encountered serious technical obstacles.

In order to break through these bottlenecks, the industry began to introduce new materials and technologies, such as high-k dielectric materials and extreme ultraviolet (EUV) lithography equipment. High-k materials can increase the capacitance of capacitors without increasing the size of capacitors by increasing the dielectric constant of dielectrics, thereby alleviating the problem of capacitance drop caused by the reduction of dielectric thickness. EUV lithography technology uses extremely short wavelength beams to accurately etch patterns on a smaller scale, making higher density transistor layouts possible. However, the introduction of these new technologies is not without cost. They are usually accompanied by huge R&D investment and manufacturing costs, and also put forward higher requirements for process control.

As the difficulty of 2D DRAM scaling increases, the entire industry has increasingly prominent problems in R&D investment, manufacturing costs, and yield control. Although further miniaturization of technology nodes can increase more bit storage capacity per unit area, the investment required shows nonlinear growth, and performance improvement and cost savings may not achieve the expected results. This cost-effectiveness imbalance means that it is no longer economically feasible to continue to use the traditional path for DRAM scaling, which has become an unavoidable financial problem in the industry.

3D DRAM

2.1 3D DRAM

Driven by the current wave of artificial intelligence (AI) applications, the demand for high-performance memory continues to rise. HBM (High Bandwidth Memory), as a leading technology in the DRAM field, is highly sought after by the market. However, as market demand continues to expand, memory manufacturers are brewing a new round of DRAM technology "revolution" to better meet future needs. HBM technology has started the 3D process of DRAM, enabling it to develop from the traditional two-dimensional (2D) structure to three-dimensional (3D). However, although HBM has certain 3D characteristics, it cannot be fully recognized as a true 3D DRAM technology.

In the process of 3D DRAM research and development, Samsung's 4F Square VCT DRAM technology has shown characteristics that are closer to the concept of 3D DRAM. This technology significantly increases the storage capacity per unit area and improves storage efficiency by vertically stacking storage cells. Unlike the horizontal placement of storage cells in traditional DRAM, 3D DRAM can integrate more storage cells within a limited chip area by vertically stacking, thereby greatly improving storage density and performance. This technology not only provides a new path for increasing memory capacity, but also lays a solid foundation for storage needs in future high-performance computing scenarios.

Although Samsung's 4F Square VCT DRAM points the way for the development of 3D DRAM, it is not the only form of 3D DRAM technology. Memory manufacturers have more diverse visions for the development of 3D DRAM, including exploring different materials, structures, and manufacturing processes to further optimize storage performance and cost-effectiveness. In these visions, 3D DRAM is not limited to the current technical concepts, but will gradually evolve into a more mature and versatile storage solution as technology advances. At present, 3D NAND Flash has been commercialized and occupies an important position in the storage market. However, 3D DRAM technology is still in the research and development stage, but its future prospects are broad. With the vigorous development of fields such as AI and big data, the demand for large-capacity, high-performance memory will increase significantly, and 3D DRAM is expected to become the mainstream product in the future memory market. Compared with traditional DRAM, 3D DRAM not only has significant advantages in storage density and speed, but also shows good potential in energy consumption and cost control.

The development of 3D DRAM technology will become one of the key trends in the memory market. It will not only meet the current market demand for high-performance memory, but will also promote technological progress in the entire semiconductor industry. As the technology gradually matures and its application scenarios continue to expand, 3D DRAM is expected to occupy a core position in the next-generation computing architecture and become an important engine for the development of cutting-edge fields such as AI, cloud computing and big data. Memory manufacturers will continue to invest a lot of resources in this field to promote technological breakthroughs and innovations and provide strong support for the storage needs of the future digital world.

2.2 DRAM structure needs improvement

(1) To advance the scaling of DRAM, placing traditional two-dimensional (2D) DRAM components on their side and stacking them vertically has become a key strategy. However, this approach has encountered multiple technical challenges in practical applications. First, the horizontal etching involved in the stacking process is extremely difficult. Due to the significant difference in groove size, the precise control of lateral etching becomes complicated, which may affect the integrity and performance of the structure. Second, different materials need to be used during stack etching and filling, which increases the complexity of the manufacturing process. In addition, there are integration challenges when connecting different 3D components. How to achieve stable connection while maintaining performance becomes the key.

To address these challenges, some innovative approaches have been taken to improve the scaling of DRAM. First, shortening the length of capacitors and stacking them vertically is an effective way to increase storage density. Traditionally, the length and height of capacitors are equal, but by shortening the length of capacitors, more storage cells can be added in a limited space, thereby increasing the storage capacity per unit area. To achieve this, the bit line is moved to the other side of the nanosheet in the design, allowing the current to pass through the entire nanosheet through the transistor gate. This not only increases the space for capacitor processing, but also effectively reduces the occupied area of the silicon area.

Secondly, gate-all-around transistor technology was used to further reduce the active area of silicon. This design optimizes space utilization, allowing more transistors to be integrated into a smaller area. In addition, the circuit layout was further optimized by designing the once narrow and tall capacitors into short and wide structures. This improvement was achieved by moving the bit lines to the center of the architecture, freeing up more space for capacitors and transistors.

On this basis, higher integration is achieved by placing more transistors and capacitors on both sides of the bitline contact. This reconfigured nanosheet can be further stacked to increase the number of transistors and capacitors on each bitline contact. In the first iteration, the vertically stacked 3D DRAM structure can reach multiple layers of height, several levels higher than the existing process node, significantly improving the storage density and capacity. As the number of stacked layers increases, the storage density of DRAM will be further improved to meet the future demand for memory for high-performance computing and big data processing.

(2) The development of 3D DRAM requires not only a completely new architectural design, but also major improvements in metallization and connectivity. In order to achieve efficient current transmission in the vertical direction, engineers have explored several new methods that allow current to pass through the central bitline stack to activate specific storage layers. One of the methods is to use a horizontal MIM (metal-insulator-metal) capacitor array to connect the storage cells at each layer, while introducing a gate-all-around (GAA) structure to completely wrap the gate material around the silicon transistor. When current passes through these bit lines, only the bit lines in the target layer are activated, ensuring that the current can be accurately connected to the required transistors, thereby achieving accurate read and write operations.

The key components of 3D DRAM include multi-layer stacked gates that fully surround nano-thin silicon transistors, bitline layers between two rows of transistors, 24 vertical wordline bitlines, interconnection levels between layers, and MIM capacitor arrays. These designs not only improve the storage density of 3D DRAM, but also enhance its performance and efficiency. In order to overcome the limitations of the step-type structure in traditional 3D NAND, 3D DRAM introduces a new through-hole array structure. These through-holes pass through the silicon stack layers and stop at specific storage layers, forming a unique design of one through-hole per layer, so that the contact point can be directly located inside the storage cell. This structure simplifies the connectivity of 3D DRAM while improving the controllability and stability of manufacturing.

In the actual manufacturing process, trench production is a key step. First, the trench is made and the isolation layer is introduced on the sidewall, and then the etching dielectric is introduced using the high trench structure to remove unnecessary silicon material. Next, the conductive metal is filled into the empty trench to form an effective current conduction path. This process ensures that each memory cell in the 3D DRAM can be precisely controlled and operated, thereby improving the overall storage density and performance.

Since the manufacturing process of 3D DRAM has many similarities with 3D NAND, the storage density of 3D DRAM is expected to increase synchronously with the increase in the number of 3D NAND layers. In other words, the actual density of 3D DRAM depends largely on the progress of 3D NAND technology during the same period. This correlation allows us to make reasonable predictions about the storage density of future 3D DRAM based on the existing 3D NAND technology roadmap. With the continuous advancement of 3D NAND technology, 3D DRAM is also expected to achieve higher storage density and stronger performance in the future to meet the growing demand for memory in fields such as high-performance computing, big data processing and artificial intelligence.

DRAM Technology Development Prospects

3.1 DRAM Commercial Market

The advantage of 3D DRAM lies not only in its larger capacity, but also in its excellent data access speed. Traditional DRAM needs to go through a multi-step operation process when reading and writing data, which usually includes data addressing, access and refresh operations, which may lead to access speed limitations. However, 3D DRAM allows data to be read and written more directly through a vertically stacked storage cell structure. This vertical access method significantly simplifies the data flow path, reduces latency, and greatly improves data access speed, thus showing significant advantages in high-performance computing and real-time processing applications.

In addition to the speed improvement, 3D DRAM also has the characteristics of low power consumption and high reliability. In traditional DRAM, in order to maintain data stability, the circuit needs to be refreshed frequently, resulting in higher power consumption. However, 3D DRAM can significantly reduce power consumption due to its efficient storage cell structure and optimized current path design, making it more suitable for energy-sensitive application scenarios such as mobile devices and embedded systems. In addition, the vertical stacking design of 3D DRAM allows it to accommodate more storage cells in a smaller space, which not only improves storage density, but also enhances its anti-interference and durability, thereby ensuring stable operation in harsh environments.

Currently, multiple concepts around 3D DRAM technology have been proposed, and related technologies have been applied for patent protection. This shows that 3D DRAM is gradually moving from theoretical concepts to practical applications. Major DRAM manufacturers are actively conducting wafer-level tests to verify and optimize the performance and manufacturing process of 3D DRAM. These tests are not only aimed at ensuring the feasibility of 3D DRAM, but also preparing for mass production and market promotion.

Industry-leading manufacturers are increasing their investment in the research and development of 3D DRAM technology and consolidating their position in future market competition through patent layout. This strategy shows that 3D DRAM technology is not only strategically important, but also has huge commercial potential. In the future, as 3D DRAM technology matures and its application scenarios expand, it is expected to become a mainstream product in the storage market, promoting innovation and development of the entire memory industry. Through patent protection and technology reserves, manufacturers not only lay the foundation for future market dominance, but also provide strong guarantees for the development of technology. Over time, 3D DRAM will become an important part of high-performance storage solutions, providing strong support for various computing and data processing tasks.

3.2 Technical Challenges of 3D DRAM

Although 3D DRAM technology has demonstrated many advantages and made significant progress, it still faces a series of technical bottlenecks and challenges in its march toward large-scale applications. In the process of transitioning from 2D DRAM to 3D DRAM, the process and technical complexity involved has increased significantly. First, 3D DRAM faces challenges in terms of fault tolerance and stability. In a multi-layer stacked 3D DRAM, the failure of a single memory cell may affect the reliability of the entire stack, so special attention must be paid to improving the fault tolerance of the memory cell during the design and manufacturing process to ensure data reliability. This may require the use of more advanced error correction technology and redundant design to mitigate the impact of failures on the system as a whole.

At the same time, signal transmission and interconnection are also key issues in the development of 3D DRAM. In a multi-layer stacking structure, data needs to achieve high-speed signal transmission between different layers. However, since the signal transmission process may be affected by delays and interference, how to improve the efficiency of signal transmission and reduce interference has become a key factor in determining the performance of 3D DRAM. This requires the use of more advanced interconnection technology and high-frequency signal processing methods to ensure the stability and speed of data transmission. In addition, as the number of layers of 3D DRAM memory increases, heat dissipation and temperature management issues have become more prominent. The design of the stacking structure makes it easy for heat to accumulate inside the memory, and excessive temperature may cause performance degradation and even shorten the service life of the memory. Therefore, how to effectively dissipate heat and manage temperature has become an important problem that must be solved in the design of 3D DRAM, which may require the use of new materials, optimized packaging design and advanced thermal management technology to effectively disperse and manage heat.

Manufacturing complexity and cost are also challenges that cannot be ignored in the development of 3D DRAM. The manufacture of 3D DRAM involves more complex process steps than traditional 2D DRAM, including vertical connection and multi-layer stacking, which not only increases the technical difficulty of manufacturing, but also significantly increases production costs. Therefore, how to ensure performance while controlling manufacturing costs has become a key issue for the large-scale commercial application of 3D DRAM. In addition, the advancement of packaging technology is also crucial. Since the structure of 3D DRAM is more complex, how to effectively package these memories to meet market demand is a major challenge. The packaging needs to provide not only physical protection, but also ensure the reliability of electrical connections and have good heat dissipation performance.

Driven by emerging applications such as AI, cloud computing, and autonomous driving, 3D DRAM has broad development prospects. In the next few years, 3D DRAM technology will continue to develop in terms of increasing the number of stacking layers, improving storage density, accelerating data transmission speed, reducing power consumption, and integrating functions. These advances will bring more efficient and high-performance storage solutions to various fields. Although 3D DRAM is still in the early stage of industrialization and the market structure is not yet fully clear, it is foreseeable that 3D DRAM will become an important turning point in the memory market, providing storage manufacturers with new opportunities to seize the strategic heights of the future. In this process, 3D DRAM is expected to become an important force in promoting the revolution of storage technology.

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3.3. 3D DRAM layout of leading companies

(1) At Memcon 2024, a global chipmaker summit in March 2024, Samsung Electronics detailed its 3D DRAM development roadmap. The announcement marks Samsung's continued advancement and strategic layout in 3D DRAM technology. As early as 2021, Samsung officially launched its 3D DRAM development project. At this summit, Samsung revealed its technology development plans and goals for the next few years.

Samsung plans to launch an early version of 3D DRAM based on vertical channel transistor technology in 2025. The key to this new technology is that the direction of the channel in its transistor structure is changed from the traditional horizontal to vertical, and a gate is used to wrap the channel as a switch. The design of the vertical channel transistor can not only significantly reduce the area occupied by the device, but also improve storage density and performance. However, this design requires higher precision in the etching process, which poses greater challenges to the manufacturing process.

In 2030, Samsung also plans to launch an updated version of stacked DRAM, which will stack all storage cells, including capacitors, vertically. The stacked DRAM design allows full utilization of the Z-axis space within a limited plane space, thereby achieving a storage capacity of more than 100GB on a single chip. This design not only significantly improves storage density, but also meets the growing demand for data storage.

To promote the development of 3D DRAM technology, Samsung earlier established a new R&D laboratory in Silicon Valley, USA. The laboratory is dedicated to developing and optimizing 3D DRAM technology, including two key technologies: vertical channel transistors and stacked DRAM. Samsung also demonstrated how to manufacture these 3D DRAM chips through advanced wafer-to-wafer hybrid bonding technology. In addition, Samsung is exploring the application of back-side power supply network (BSPDN) technology to 3D DRAM to further improve its performance and efficiency. These technological innovations and R&D progress show that Samsung is actively promoting the industrialization of 3D DRAM and striving to take a leading position in the future storage market. These efforts not only demonstrate Samsung's deep strength in storage technology, but also reflect its forward-looking layout for future storage needs and technology trends.

(2) Micron has been actively conducting research on 3D DRAM since 2019 and has made significant progress in this technology field. As of August 2022, Micron has obtained more than 30 patents related to 3D DRAM, which is two to three times the number of major Korean chip manufacturers such as Samsung Electronics and SK Hynix. These patents of Micron cover all aspects of 3D DRAM technology, reflecting its technical depth and innovation capabilities in this field.

Micron believes that 3D DRAM will be an important direction for the development of DRAM technology and regards it as a key step in the expansion of future storage technology. To achieve the goal of 3D DRAM, the entire semiconductor industry is actively conducting relevant research. These studies involve multiple technical fields, including the development of manufacturing equipment, advanced atomic layer deposition (ALD), selective vapor deposition (CVD), and selective etching processes. In addition, discussions on 3D DRAM architecture are also advancing, aiming to optimize the performance and density of memory.

According to the analysis of industry research company Yole, Micron's 3D DRAM patent application is different from Samsung Electronics' solution. Micron's technical solution changes the shape of transistors and capacitors instead of placing additional capacitors in the memory cell. The core of this approach is to optimize the geometric design of transistors and capacitors to improve storage density and performance. This innovative design idea may provide new solutions for the implementation of 3D DRAM technology and promote the further development of storage technology.

Overall, Micron's investment and innovation in 3D DRAM technology demonstrate its strategic positioning in the future storage market. With the continuous advancement of technology and the accumulation of patents, Micron has not only achieved a leading edge in the field of technology, but also laid a solid foundation for future market competition. This technology-driven and innovative strategy will have a profound impact on the development of the memory industry.

(3) NEO Semiconductor has launched a new technology called 3D X-DRAM, which aims to break through the capacity limitations of traditional DRAM. 3D X-DRAM uses a cell array structure similar to 3D NAND Flash, but its core innovation lies in the use of FBC (capacitor-free floating cell) technology. Unlike traditional DRAM, 3D X-DRAM introduces multiple layers of masks in the transistor structure to form vertically stacked memory cells, thereby achieving higher storage density and lower manufacturing costs. This design not only improves production yield, but also significantly reduces production costs, making 3D X-DRAM an effective solution to meet the growing demand for storage.

NEO Semiconductor said that 3D X-DRAM technology can produce 128Gbit DRAM chips with up to 230 layers, which is eight times the density of current DRAM technology. This breakthrough enables 3D X-DRAM to provide extremely high storage capacity in a relatively small space, thus meeting the growing demand for high-performance, large-capacity memory. In particular, with the rapid development of AI applications (such as ChatGPT), the performance and capacity requirements for memory are also increasing, and the introduction of 3D X-DRAM is precisely to meet this challenge.

In addition to the significant increase in capacity, 3D X-DRAM also solves the challenges faced by traditional DRAM technology in the high-density stacking process, such as heat dissipation and production complexity. Its vertical structure design helps to better manage heat while simplifying the manufacturing process, making the technology more mature and economical. Therefore, 3D X-DRAM not only provides innovative solutions at the technical level, but also becomes an important direction for future memory development driven by market demand.

References: Huaxin Securities, Yushi Capital Research Institute

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