The semiconductor supply chain reported at the end of last year that TSMC's 2nm trial production yield exceeded 60%, better than expected, and mass production will be on schedule in 2025. A netizen who claimed to be a TSMC employee pointed out on a social platform that TSMC is expanding its 2nm production capacity with a goal of producing more than 100,000 wafers per month.

This newspaper previously disclosed that TSMC's 2nm adopts the Nanosheet architecture for the first time, which has a higher technical threshold and is more complex than the current 3nm FinFET process technology. It is currently conducting risky trial production at the first plant in Baoshan, Hsinchu Science Park. When the yield reaches the mass production level, the mass production experience will be replicated to the first plant in Kaohsiung for mass production.

TSMC does not disclose the trial production yield, but only emphasizes that the current 2nm is progressing smoothly and will be mass-produced as scheduled in 2025, which will be the industry's most advanced technology. The semiconductor supply chain reported that TSMC's 2nm trial production yield exceeded 60%, which is better than expected.

Recently, it was reported that TSMC's 2nm monthly production capacity is expected to be 50,000 pieces by the end of the year, and if progress is smooth, it is expected to reach 80,000 pieces. Regarding the above rumors, a netizen Dr. Kim who claims to be a TSMC employee posted on the social platform X that the information is true, and said: "We are expanding the production capacity of 2nm, with the goal of producing more than 100,000 pieces per month."

2nm, the battle to the top

In addition to TSMC, Samsung and Intel are also working on 2nm.

According to well-known analysis agency TechInsights, Intel's 18A can provide higher performance, while TSMC's N2 may provide higher transistor density. TechInsights analysts believe that TSMC's N2 provides a high-density (HD) standard cell transistor density of 313 MTr/mm2, far exceeding the HD cell density of Intel 18A (238 MTr/mm2) and Samsung SF2/SF3P (231 MTr/mm2). Although this information is roughly consistent with the SRAM cell sizes of 18A, N2 and N3, and TSMC's expectations for N2 and N3, there are still some things to note.

First, this only involves HD standard cells. Almost all modern high-performance processors that rely on cutting-edge nodes use a mixture of high-density (HD), high-performance (HP) and low-power (LP) standard cells, not to mention features like TSMC's FinFlex and NanoFlex.

Second, it is unclear how Intel and TSMC's HP and LP standard cells compare. While it is reasonable to assume that N2 leads in transistor density, its lead may not be as large as that of the HD standard cell. Third, in papers presented at the IEDM event, both Intel and TSMC disclosed the performance, power, and transistor density advantages of their next-generation 18A and N2 manufacturing processes over their predecessors. However, there is currently no way to compare the two manufacturing technologies head-to-head.

In terms of performance, TechInsights believes that Intel's 18A will be ahead of TSMC's N2 and Samsung's SF2 (formerly known as SF3P). However, TechInsights uses a controversial method to compare the performance of the upcoming nodes, as it uses TSMC's N16FF and Samsung's 14nm process technology as a baseline and then adds the node-to-node performance improvements announced by the two companies to make the prediction. While this may be an estimate, it may not be completely accurate.

On the other hand, Intel is focused on making high-performance processors, so the 18A can be tailored for performance and power efficiency rather than HD transistor density. The bottom line is that the 18A supports the backside power delivery network PowerVia, and chips using this network may have performance and transistor density advantages over TSMC's N2, which does not support this feature. However, this does not mean that every 18A chip will use PowerVia.

Speaking of power consumption, TechInsights analysts speculate that N2-based chips will consume less power than similar ICs based on SF2, as TSMC has been leading in power efficiency in recent years. As for Intel, that remains to be seen, but at least the 18A will offer an advantage in this regard.

Another widely circulated number is that TSMC's 2nm process will cost $30,000 per wafer.

TechInsights provides the world's leading semiconductor cost and price model. Before 3nm went into production, we expected a cost of less than $20,000 per wafer, and some customers contacted us insisting that 3nm would cost $20,000 to $25,000 per wafer. After 3nm went into production, we were able to conduct proprietary forensics on TSMC's financials and determined that we were correct and that volume prices were less than $20,000 per wafer, a difference of thousands of dollars.

Going from less than $20,000 per wafer for 3nm to $30,000 per wafer for 2nm represents a price increase of more than 1.5 times, a 1.15 times increase in density, and a significant increase in transistor cost, which raises the question: Who will pay for this? Our price estimate is less than $30,000 per wafer. There are also reports that Apple, typically a major customer at each node for TSMC, may move away from initial 2nm use for price reasons, although we have also heard objections.

Another element to this discussion is that TSMC's high-volume wafer prices are much lower than low-volume wafer prices, so volume needs to be considered in any discussion. Overall, we believe that $30,000 is above average to high-volume pricing.

If TSMC prices 2nm wafers at $30,000 per wafer, they will put a lot of pressure on customers to turn to Intel and Samsung for 2nm-class wafer supply.

Reference link https://www.tomshardware.com/tech-industry/intels-18a-and-tsmcs-n2-process-nodes-compared-intel-is-faster-but-tsmc-is-denser

Source: Content from Semiconductor Industry Observation

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