In 2023, generative AI is like a hot fried chicken, attracting global attention. At present, the competition around this field is becoming more and more fierce, and the world is caught in a war of 100 models, and is striving towards the war of 1,000 models. In this trend, AI chips have become the supporting engine, providing strong support for large-scale model applications. The special requirements brought about by the vigorous development of large-scale model applications are driving the chip design industry into a new era. Many top semiconductor manufacturers have specially built AI chips for large-scale applications. Its high computing power, high bandwidth, and the number of transistors in the hundreds of billions have become standard configurations for large chips.

Chip design complexity, towards a new peak

In the field of artificial intelligence, the rise of large-scale model applications has brought the development of chips to a new level. Large-scale model applications need to process large-scale data. OpenAI's ChatGPT has developed from about 5 billion parameters in the first generation to GPT4.0 with parameters that will exceed 1T. Needless to say, there is a high demand for computing power. In addition, HBM has been introduced by major chip manufacturers as a high-performance memory solution. At the same time, advanced packaging technologies such as CoWoS have become the mainstream choice for GPUs. Advanced packaging technologies and HBM are a combination that cannot be ignored. Through multi-  chip stacking, the communication speed and energy efficiency between chips are improved, providing powerful support for large-scale applications. support.

Chiplet technology is considered to be one of the important technologies to continue to increase computing power density in the post-Moore era, and it has also won the favor of large-scale AI chips. Chiplet technology divides the chip into smaller modules, so that the chip can adopt a heterogeneous design, that is, different modules can be provided by different manufacturers, which brings greater flexibility and innovation space for chip design. Chiplet technology is changing the semiconductor industry, and its application potential is limitless. According to a report by research firm Omdia, the global market for chiplet-based processor chips will reach $5.8 billion in 2024 and $57 billion in 2035.

The chip design behind the large model application shows an obvious trend: the chip is no longer a simple integrated circuit, but a multi-dimensional interweaving product, including a new architecture design, innovative interconnection methods, and advanced packaging technologies, etc.

However, the challenges of the chip design industry are not limited to the rapid development of large model applications. With the development of application markets such as smartphones, Internet of Things devices, and self-driving cars, the requirements for chips in various fields are getting higher and higher. Therefore, semiconductor designers and manufacturers must use more sophisticated and complex design methods to meet these new demands.

In the field of consumer electronics, many mobile and handheld devices have very urgent requirements for low power consumption. In order to achieve low-power design goals, chip designers have to adopt advanced low-power technologies, including power-off technology (PSO), multiple supply voltage (MSV) and dynamic voltage frequency scaling (DVFS) and other technologies.

In the automotive industry, in order to meet the needs of the development of modern vehicles "electrification, networking, intelligence, and sharing", the processors required in automobiles are becoming more and more powerful, and the requirements for safety are also getting higher and higher. However, high-performance processors also pose higher security risks. Therefore, the design and implementation of these processors must be more rigorously tested and verified.

Simulation, the Pioneer in Solving Complex Chip Verification Challenges

As various applications put forward new requirements for chips, the complexity of chip design is increasing at an unprecedented rate, which not only leads to a sharp expansion of trial and error costs, but also brings severe challenges to verification work.

With the sharp increase in the number of transistors and the introduction of new architectures and designs, designers are faced with more and more verification scenarios, and the factors considered are also continuously expanding. For example, the emerging chiplet design method brings new verification and debugging challenges: designers must ensure that the modules can work together seamlessly after combination, and once an error occurs, it is necessary to accurately locate the source of the problem when debugging the problem.

Before the final tape-out is decided, a comprehensive functional verification and performance evaluation to eliminate all potential defects and hidden dangers is the decisive factor to avoid huge losses in the later stage of production. In the battle against this growing verification complexity, the role of emulators is being given increasing value and anticipation.

As a tool to verify the function and performance of chip design, the emulator provides chip designers with a virtual environment for simulating circuit operation, helping to predict and solve potential problems, and avoiding errors from entering the actual manufacturing process, thereby saving time and cost. Emulators will be at the vanguard of solving many of the challenges of complex chip design.

With the emergence of new technologies, in order to meet the ever-increasing verification requirements, simulation tools need to provide efficient simulation performance, actively explore and introduce new technologies, such as hardware acceleration and machine learning, so as to improve the efficiency and accuracy of verification. In addition, simulation tools need to have good scalability, be able to handle large-scale designs, and support parallel computing and distributed simulation.

To meet the challenges of new technologies, simulation to achieve re-evolution

When it comes to simulation, we have to talk about Cadence, a giant in the EDA industry. Since the mid-to-late 1980s, Cadence has creatively launched the Verilog language, providing digital circuit designers with a standard language for describing and verifying circuit behavior, which greatly improves the efficiency and accuracy of design. Cadence even made the Verilog language freely available to the industry, furthering the advancement of digital circuit design.

Today, however, Cadence's Xcelium Logic Simulator simulator is expected to become a powerful assistant for complex chip verification. This emulator not only has excellent performance and large capacity, but also supports multiple language types, including SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards. By taking full advantage of constraint information, constraint performance analysis, and debugging capabilities, the Xcelium simulator achieves significant speedups in verification at the IP level, powering next-generation chip designs.

Xcelium Logic Simulator leverages its parallel and incremental build technology to dramatically reduce build times, lower compile memory footprint, and reduce storage space required for designs. In addition, Xcelium has a leading one-stop front-end compiler in the market, covering the entire verification process from software to hardware simulation. Furthermore, the multi-core engine used by Xcelium brings speed improvements to time-consuming test projects. Its advanced save/restore technology enables it to support digital and real number simulation, as well as analog mixed-signal simulation. Xcelium is also equipped with functions such as dynamic test loading, constraint solver optimization and multi-thread parallel processing to improve simulation efficiency.

The beauty of Xcelium is that it implements a series of beneficial extensions in the native engine of Xcelium Logic Simulator, including machine learning, functional safety, multi-core, mixed signal, power playback, X-Pessimism Removal, etc. The combination of these six Apps is almost Covering various technologies in the design and verification cycle, it can be described as all-encompassing.

For example, in the chip design process, design verification engineers often have to work overtime and run countless regressions, consuming their minds to achieve coverage goals. Even if a lot of manpower and time are invested in verification, there is a risk of functional failure during tape-out Also very high. In response to this problem, Xcelium's machine learning App (Xcelium Machine Learning) introduces Cadence's proprietary machine learning technology, which can not only accelerate coverage convergence, but also learn from previous regression runs and guide the Xcelium random engine to achieve the same Under the premise of coverage, the number of simulations can be greatly reduced, which can be reduced by up to ten times, or incentives can be generated at specific coverage points to find more vulnerabilities. With fewer simulations and more precise test stimuli, engineers can focus on finding and resolving design issues rather than being bogged down by repeated regression runs.

                                                    Xcelium ML pipeline

As another example, for functional safety in automobiles, Cadence's Xcelium is the only simulator on the market that enables concurrent injection in the main engine, and the Xcelium Safety App supports both serial and parallel fault simulation. Combined with Cadence safety verification full-flow tools such as Jasper Safety, vManager Safety, and Midas Safety Planner, Xcelium can efficiently perform safety fault injection to meet the requirements of the ISO26262 standard. In addition, Cadence offers an extensive suite of automotive functional safety documentation covering the full spectrum of semiconductor design and verification. The kit significantly reduces suppliers' effort to conduct tool use-case evaluations in each automotive design project and helps them avoid costly tool certification efforts.

          Cadence Xcelium Fault Simulation Solution for ISO 26262 Compliant

For chip companies that want to take the Chiplet route, Xcelium's multi-core application (Multi-Core App) is a highly scalable solution for accelerating gate-level simulation. It automatically decomposes chip designs into independent parts and simulates them on the server's parallel cores, greatly reducing the simulation time of SystemVerilog designs, especially for large-scale designs.

Overall, we are in a period of change in the chip industry where innovation and speed are the keys to success. The rapid development of new technologies and the continuous emergence of new requirements have led to an exponential increase in the complexity of chip design. In this process, how to improve production efficiency and how to shorten the time to market are challenges for design engineers. The intervention of the emulator will be an effective tool for chip manufacturers to explore new technologies and solve complex chip design problems.

It is believed that with the combination of Xcelium Logic Simulator and various Apps, large and small chip companies can more confidently meet the complex challenges in the design process of the new generation of chips, quickly promote design verification, and quickly introduce innovative products to the market. Forward into the further future.

About Cadence

Cadence is a key leader in electronic systems design with more than 30 years of computing software expertise. Based on the company's intelligent system design strategy, Cadence is committed to providing software, hardware and IP products to help electronic design concepts become reality. Cadence customers around the world are some of the most innovative companies delivering everything from chips to boards to some of the most dynamic application markets, including hyperscale computing, 5G communications, automotive, mobile devices, aerospace, consumer electronics, industrial and medical. Superior electronics to complete systems. For the ninth year in a row, Cadence has been named to Fortune Magazine's 100 Best Companies to Work For.