Recently, the RISC-V instruction set architecture has once again made a strong breakthrough under the spotlight of the global semiconductor industry! According to Reuters on March 4, China plans to issue guidelines for the first time to promote the use of open source RISC-V chips nationwide and accelerate the industrialization of RISC-V technology. At the same time, the European High Performance Computing Agency (HPC) consortium launched the DARE project, planning to invest 240 million euros to develop AI chips and software for the RISC-V architecture. After 15 years of development, RISC-V is changing the landscape of the global semiconductor industry at an astonishing speed. From the high-performance processor C930 that Alibaba Damo Academy is about to deliver, to the progress of Xinlai Technology in the fields of AI and automotive electronics, to the breakthrough of micro-core high-performance server chips, RISC-V is leading a technological revolution. This revolution is not only reflected in the leap in performance, but also in its open and free characteristics, which provide unprecedented opportunities for countless innovators.

Why choose RISC-V for the dimensional war? 

The industrial evolution of processor architecture has always followed the iron law of "scenario-driven technology". In the late 1970s, Intel built the computing power base of the PC era with the x86 architecture, laying the foundation for the industry for 40 years; in the early 21st century, in the wave of mobile Internet, ARM opened a new era of mobile terminal processors with its energy efficiency-first architecture philosophy.

However, although these two systems have dominated the market for a long time, they have buried dual structural contradictions. At the industrial level, the monopoly of instruction set standards has led to the reverse of the "hardware defines software" ecosystem. Users need to modify their needs to adapt to the processor, and the optimization of scenario-based applications is limited; at the technical level, the need to cover all scenarios has generated a lot of cost redundancy such as power consumption redundancy. When the computing paradigm enters a new stage dominated by cloud native and AI big models, architectural innovation has ushered in a triple breakthrough window. Heterogeneous computing has given rise to the dynamic coordination needs of CPUs and AI accelerators, and the refinement of industry scenarios has forced the granularity of architectural design to increase by 2-3 orders of magnitude. In this context, the RISC-V open instruction set has shown its potential to break through: its modular architecture supports agile customization from AI reasoning units to domain-specific processors, and breaks the 40-year standard monopoly of instruction set architecture through an open source ecosystem. Omdia predicts that from 2024 to 2030, the shipment of RISC-V-based processors will grow at a rate of nearly 50% per year, and it is expected that the shipment will reach 17 billion by 2030, accounting for nearly a quarter of the global market. It is worth noting that my country's semiconductor industry has demonstrated a unique strategic path in this architectural revolution. Beijing Microcore Technology Co., Ltd. (hereinafter referred to as Microcore), established in 2020, is a typical example. At that time, 90% of global RISC-V developers focused on the low-end AIoT market, while this Chinese chip forward-lookingly locked in the two high-end tracks of server and AI computing - this is precisely the key battlefield to break through the overseas technology blockade and the must-win place to achieve autonomous and controllable architecture.

Technology accumulation and innovative breakthroughs

In the semiconductor industry, each generation of architectural breakthroughs requires decades of experience. The MicroCore team has accumulated more than 20 years of industry know-how and successfully achieved a leap from technology parallel to realization. Its independently developed high-performance processor SPEC CPU2006 score reached 15 points/GHz, and its performance is comparable to ARM's latest server chip N2. According to reports, this team technically covers all areas of high-performance processor development, including the entire process of architecture design, verification, physical implementation and software. Therefore, they have sufficient capabilities to provide a "family bucket" server system solution, high-performance CPU core + on-chip network (NoC) multi-core interconnection + SoC architecture, and combined with Chiplet technology, it greatly reduces the design and manufacturing costs of chips and accelerates the speed of chip R&D iteration.

Taking the GKG series of products as an example, this high-performance RISC-V chip integrates multiple independently developed high-performance processor cores and adopts an out-of-order multi-issue superscalar pipeline. Based on the RISC-V basic instruction set, it supports hardware virtualization, vectors, AI and other high-performance instruction set extensions. It has the advantages of high performance and low power consumption, and has completed large-scale commercial deployment in servers, terminal devices, embedded equipment, industrial control and other fields, demonstrating the innovative potential of the RISC-V architecture in high-performance computing scenarios.

In MicroCore's view, behind these achievements is the continuous evolution of two core capabilities: the first is the "global optimization" capability: the unique ability to coordinate architecture design and process evolution, and the independent control of the entire process from chip architecture design to process implementation, so that chips with better power consumption and stronger performance can be made, while greatly shortening the development cycle. The second is the "tailor-made" capability: customize the chip architecture according to the specific needs of customers, uniformly optimize and decompose the task indicators of each stage, and through reasonable scheduling of resources, give full play to the performance of the process and ensure that the performance of the processor is sufficiently competitive. Because of this, MicroCore has formed a technological moat in just a few years, has applied for more than 70 Chinese invention patents, and has obtained authorization for multiple core patents in the United States, Europe and other places.

With its profound technical accumulation, MicroCore has continuously improved its customized services and launched a RISC-V high-performance processor customization platform. The platform covers RISC-V high-performance processor cores, network-on-chip (NoC) multi-core interconnection, SoC architecture and software platform, and can provide users with comprehensive hardware and software unified optimization of the best chip solution. Among them, the key high-performance processor cores, NoC multi-core interconnection and SoC architecture are all self-developed, supporting customization of multiple performance levels, and can be deeply optimized according to user needs. The RISC-V high-performance platform has a wide range of applications, suitable for many fields such as data center servers, robots, autonomous driving, and high-density computing clusters.

Breaking into the technical no-man's land of X86/ARM

The wave of technological innovation will inevitably encounter challenges in commercialization in the process of breaking through to the heights of industrialization. Obviously, Microcore is ready to respond. They adopt a strategy of deep integration with applications to do "what X86 and ARM want to do but cannot do." The core challenges of the current large-scale commercialization of the RISC-V architecture focus on two dimensions, and its breakthrough path is systematically presented as: the construction of an ecological trust system and a precise breakthrough strategy for differentiated tracks. Specifically, the establishment of ecological confidence can be built through policy coordination mechanisms, closed loops of technical verification, and industrial collaboration networks. Breakthroughs in differentiated tracks can target opportunities for computing power reconstruction, emerging fields, and demand-driven development. This is also the commercialization path that Microcore has been exploring: by building a three-dimensional ecological system guided by policies, led by enterprises, and supported by colleges and universities, a breakthrough trend has been formed in trillion-level markets such as intelligent computing, automotive electronics, and industrial automation. The core element lies in accurately grasping the rigid demand gap of the X86 and ARM architectures, transforming the architectural freedom of RISC-V into a scenario adaptation advantage, and ultimately realizing a closed-loop transformation from technical advantages to commercial value.

A tsunami has been set off in the deep waters of AI computing power

Today, the wave of AI technology has swept the world, algorithm innovation has accelerated breakthroughs, and application scenarios have deeply penetrated into core business areas. How to build a systematic strategic framework for the AI era has become a key proposition for corporate strategic planning. In the evolutionary map of ubiquitous technology, RISC-V and AI technology show significant common characteristics-both belong to underlying architectural innovations, and their true value release needs to be achieved through the deep integration of vertical scenarios. Faced with the generational gap between the domestic semiconductor industry in advanced processes and ecological chains, MicroCore chooses to focus on scenario-driven architectural innovation. Taking the field of humanoid robots as an example, its technical demand matrix includes three core dimensions: energy efficiency constraints, real-time multimodal interaction, and cognitive intelligence realization. The existing general computing architecture is difficult to meet such complex technical indicators, which is the opportunity window for the collaborative innovation of RISC-V open instruction set and AI acceleration architecture.

The development of AI chips requires reasonable optimization and customization of chips according to application requirements to achieve a balance between general and special purposes. Microcore points out the split in traditional architecture: the CPU executes control flow, and AI (or GPGPU) executes data flow; but in actual applications, there is no absolute data flow, nor absolute control flow, but more of a combination of the two and different proportions for different fields. The decomposition and scheduling of tasks are the key to determining chip system solutions, which requires deep binding of applications and chip designs to achieve, so a collaborative framework for CPU and AI must be designed. At the same time, the software and hardware collaborative framework is particularly important, and it is necessary to deeply decompose the application and computing framework, data flow and control flow from the application perspective.

MicroCore has proposed a three-level CPU+AI collaborative framework: 

• Solution 1: Integration of AI acceleration modules within the SoC framework; 

• Solution 2: AI instruction extension at the CPU level;

• Solution 3: AI coprocessor design within the CPU framework.

In the existing market, most chip solutions adopt Solution 1 and Solution 2. Solution 1 has high AI execution efficiency, but its adaptability to future applications is poor, and its integration with control flow is weak, and it can only interact with the CPU at the memory level. Solution 2 has the best application adaptability, but the lowest AI execution efficiency, and is limited to special application fields where control flow is the main and data flow is the auxiliary. Solution 3 is based on a high-performance CPU framework, which retains the characteristics of high-performance CPU control flow execution capabilities, and can combine the advantages of high AI execution efficiency of AI coprocessors. MicroCore believes that this is the development trend of AI chips in the future.

Source: Core Master

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