Source: Content compiled from IEEE

The semiconductor industry's long-standing law -- Moore's Law, which states that the density of transistors on a chip doubles approximately every two years -- is becoming increasingly difficult to maintain. The ability to shrink transistors and their interconnections is running into some fundamental physical limitations. In particular, as copper interconnects shrink, their resistivity rises dramatically, which reduces the amount of information they can carry and increases their energy consumption.

The industry has been searching for alternative interconnect materials to extend the progress of Moore's Law. Graphene is a very attractive option in many ways: This thin sheet of carbon material has excellent electrical and thermal conductivity and is stronger than diamond.

However, researchers have had difficulty incorporating graphene into mainstream computing applications for two main reasons. First, depositing graphene requires high temperatures, which are incompatible with traditional CMOS manufacturing. Second, the carrier density of undoped macroscopic graphene sheets is relatively low.

Now, Destination 2D, a startup based in Milpitas, California, claims to have solved both problems. The Destination 2D team has demonstrated a technique to deposit graphene interconnects onto chips at 300°C, which is still low enough to be implemented with traditional CMOS technology. They have also developed a method to dope graphene sheets that can deliver 100 times higher current density than copper, according to Kaustav Banerjee, co-founder and CTO of Destination 2D.

"People have been trying to use graphene for a variety of applications, but in mainstream microelectronics (essentially CMOS technology), people haven't been able to use it so far," Banerjee said.

The semiconductor industry's long-standing law - Moore's Law, which states that the density of transistors on a chip doubles approximately every two years - is becoming increasingly difficult to maintain. The ability to shrink transistors and their interconnects is running into some fundamental physical limits. In particular, as copper interconnects shrink, their resistivity rises dramatically, which reduces the amount of information they can carry and increases their energy consumption.

CMOS Manufacturing

The industry has been searching for alternative interconnect materials to extend the progress of Moore's Law. Graphene is a very attractive option in many ways: This thin sheet of carbon material has excellent electrical and thermal conductivity and is stronger than diamond.

However, researchers have had difficulty in bringing graphene into mainstream computing applications for two main reasons. First, depositing graphene requires high temperatures, which are incompatible with traditional CMOS manufacturing. Second, the carrier density of undoped macroscopic graphene sheets is relatively low.

Now, Destination 2D, a startup based in Milpitas, California, claims to have solved both problems. The Destination 2D team demonstrated a technique to deposit graphene interconnects onto a chip at 300°C, which is still low enough to be done with conventional CMOS technology. They also developed a method to dope the graphene sheets, which delivers 100 times higher current density than copper, according to Destination 2D co-founder and CTO Kaustav Banerjee.

"People have been trying to use graphene for various applications, but in mainstream microelectronics, which is essentially CMOS technology, people haven't been able to use it until now," Banerjee said.

Destination 2D isn't the only company pursuing graphene interconnects. TSMC and Samsung are also working to bring the technology up to par. However, Banerjee claims that Destination 2D is the only company to demonstrate graphene deposition directly on top of a transistor chip, rather than growing the interconnect separately and attaching it to the chip after the fact.

01 Low temperature graphene deposition

Graphene was first isolated in 2004, when researchers used sticky tape to peel sheets of graphene from blocks of graphite. The material was considered so promising that it won a Nobel Prize in 2010. (Nobel co-winner Konstantin Novoselov is now chief scientist at Destination 2D).

However, carefully peeling graphene from the tip of a pencil with sticky tape is not a scalable production method. To reliably make graphene structures, researchers have turned to chemical vapor deposition, which deposits carbon gas onto a heated substrate. This typically requires temperatures far above the maximum operating temperature of about 400°C in CMOS manufacturing.

Destination 2D uses a pressure-assisted direct deposition technique developed in Banerjee's lab at the University of California, Santa Barbara. Banerjee calls the technique pressure-assisted solid-phase diffusion, and it uses a sacrificial metal film such as nickel. The sacrificial film is placed on top of the transistor chip, and the carbon source is deposited on top. Then, using pressures of about 410 to 550 kilopascals (60 to 80 psi), the carbon is forced through the sacrificial metal and rejoins into clean, multilayered graphene underneath. The sacrificial metal is then simply removed, leaving the graphene on the chip for patterning. The technique works at 300°C, low enough not to damage the transistors underneath.

02 Improving graphene's current density

After the graphene interconnects are patterned, the graphene layers are doped to reduce resistivity and increase their current-carrying capacity. The Destination 2D team uses a doping technique called intercalation, in which dopant atoms are diffused between graphene sheets.

The dopant atoms can be a variety of species, such as ferric chloride, bromine, and lithium. Once implanted, the dopant donates electrons (or electron holes in the case of the material) to the graphene sheets, enabling higher current densities. "Intercalation chemistry is a very old topic," Banerjee said. "We're just bringing this intercalation into graphene, which is new."

One promising feature of this technology is that, unlike copper, as the size of graphene interconnect lines shrinks, its current-carrying capacity increases. This is because the intercalation technique becomes more efficient for thinner lines. Banerjee believes this will enable their technology to support many generations of semiconductor technology in the future.

Destination 2D has demonstrated its graphene interconnect technology at the chip level and has also developed wafer-scale deposition tools that can be implemented in manufacturing facilities. They hope to work with foundries to take their technology to R&D and, eventually, production.

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