Some time ago, the US SIA and SRC released a roadmap for the future development of semiconductors, which has been roughly described in our previous article "Semiconductor Industry, Roadmap for the Next Ten Years". At the same time, we also released the "Digital Processor Roadmap in the Eyes of Americans", and this chapter is the roadmap for the advanced packaging part of the roadmap.
Introduction
Information and communications technology (ICT) is the source of exponential growth in data that needs to be moved, stored, computed, transmitted and protected. Traditional semiconductor technology, which relies on feature size reduction, is approaching its physical limits. As transistor energy efficiency and transistor size increase exponentially, scaling system performance faces significant challenges. The speed of technology transition has slowed down to more than two years, making it increasingly urgent to achieve cost-effective packaging systems through "More Moore" traditional transistor size reduction and "More than Moore" heterogeneous integration (HI). Heterogeneous integration is critical to achieving cost and energy efficiency in next-generation computing and communications systems. Advanced packaging through heterogeneous integration offers an innovative alternative to product density and size, as Moore's Law has driven over the past 55 years. With the development of the global semiconductor industry, heterogeneous integration is and will become a key technology direction in the future.
Advances in HI technology are key to achieving the major shifts foreseeable in ICT, including:
Simulation hardware for generating smarter world-machine interfaces
Radically innovative storage solutions and memory
Hardware to address new security challenges emerging in highly connected systems
Artificial Intelligence (AI)
The energy consumption of general-purpose computing is increasing exponentially
Energy consumption doubles every three years, outpacing efficiency improvements achieved by size scaling and requiring a new computing paradigm. Therefore, the broad objectives addressed in this chapter are:
Discover computing paradigms/architectures with fundamentally new computing trajectories, achieving over 1 million times improvement in energy efficiency.
Develop technologies that integrate analog and digital systems, including neuromorphic and quantum computing, sensing, photonics, and wireless communications.
The scope of this chapter for advanced packaging and heterogeneous integration includes (but is not limited to):
Chip-package architecture and co-design
next generation interconnect technology
Power delivery and thermal management
Material
substrate
Assembly and testing
Performance and process modeling and model validation reliability
Cross-cutting activities under Advanced Packaging include:
Energy efficiency and sustainability
Supply Chain: Materials, Chemicals, Substrates
Manufacturing process and performance measurement
Security and privacy
Design modeling tests and standards
Overall, different applications require domain-specific architectures and appropriate system integration strategies to ensure signal and power integrity, power conversion and delivery, testability and security while efficiently achieving performance, power consumption, area and cost. (PPAC) trade-offs. Possible solution strategies for system integration include horizontal integration of independently produced components into higher-level SiPs, three-dimensional (3D) stacking of independent dies, and logic and storage in monolithically integrated systems on a chip (SoC) of fine layering. The architectural and physical design of SiPs requires high-fidelity and efficient modeling tools and techniques, including machine learning-based tools.
Progress toward high-density 3D system integration will increase bandwidth density and energy efficiency. Horizontal and vertical interconnect pitch scaling and next-generation interconnect technologies are key approaches to achieving high bandwidth density and energy efficiency. As I/O bandwidth will grow in proportion to the scaling of computing cores, along with exponential increases in package pin count and I/O power consumption, alternative innovation in optical interconnects is necessary as it can provide high bandwidth density, Energy efficiency and coverage.
System integration challenges require more than just chip-package co-design; it also involves packaging material selection, process development for interconnect pitch scaling, and thermal solution design while meeting reliability and manufacturing yield goals. This in turn requires advanced hotspot and defect measurement, testing and simulation to control system performance and reliability from first principles. Finally, new materials are the foundation for all innovations in interconnects, high-density substrates, thermal dissipation and emerging device development.
Chip Packaging Architectures and Codesign
Despite recent advances in monolithic chip design, scaling trends continue to lag behind the increasing demands for bandwidth, latency, and energy efficiency in artificial intelligence, high-performance computing, high-definition sensing, and other emerging applications. . In this context, technological innovation beyond monolithic chips, especially 2.5D/3D heterogeneous integration at macro and micro levels, is crucial to realizing future ICT systems with various types of chips and brings significant Performance and cost effectiveness. (Trends in advanced packaging architecture and their impact on interconnects are described in Section 7.3). This paradigm shift will drive innovation in die IP design, heterogeneous architectures, network-on-chip/package-level networking, and reliable system integration.
Some challenges and research needs include:
Chips and their signaling interfaces introduce new silicon modules into the microelectronics ecosystem with high bandwidth, high area utilization and low cost. This opens up new technologies and business models for IP reuse, allowing for flexible macro-modules with different functions. production without being limited by processing power. Such changes require design capabilities to define the interfaces between physical cores and die, as well as software and hardware co-design to classify reusable IP modules.
Close collaboration between die and package design is critical throughout the design cycle, including design tools, models and workflows. System architects must be involved early in the design process to analyze the entire system and package, partition the design into different die, and evaluate the trade-offs in compute, data transfer, and manufacturing costs. Design and verification tools at this stage, such as SystemVerilog, need to integrate package design and planning knowledge to support co-design workflows, which represents a major revision of the current separate ASIC and package design processes. Furthermore, early predictive analysis of HI systems is crucial to reduce iteration costs between (micro)architectural definition and design implementation.
Achieving chip-package co-design requires consideration of every step of the comprehensive flow, including architectural definition, RTL design, place and route, verification, and timing/power analysis. The new set of tools also needed to have smooth interfaces between each other and support future die design toolkits. HI comprehensive challenges include: timing analysis between cores, thermal/mechanical stress analysis, and power transmission and integrity of each component.
A heterogeneous system contains multiple components with significantly different electrical, mechanical, and thermal properties. Future heterogeneous system testing needs to provide sufficient modularity to accommodate specific test methods for each component, enabling a comprehensive assessment of coverage, complexity, and cost. Self-testing, such as built-in self-testing (BIST), is a desirable solution, but more research on multifunctional joint testing is needed. As the thermal/mechanical interactions between various components in 2.5D/3D integration continue to increase, reliability assessment needs to shift from the current empirical/statistical methods for individual modules to building models describing product-level physical reliability.
Next-generation Interconnects
It is well known that the cost advantages of shrinking chip size by using finer transistor nodes (sub-20nm) are no longer evident. This requires a new approach, which is to break down a monolithic chip into smaller units, or dice. In order to achieve functional expansion through HI of device dies and passive components, the substrate must transform from a chip carrier to an integrated platform, which requires new advanced packaging methods, including:
Performance Optimization: Select the best silicon process node for each IP block/die.
Product customization: By selecting the core particle combination with the best performance, each product can be customized.
Reduce costs: Compared with a single-chip SOC, a single chip has higher profits and can reduce costs.
Technology advancements in advanced packaging require new design tools that enable package design to support co-design workflows and predictive modeling to minimize iteration costs between architecture and design implementation. When designing and analyzing HI/AP systems, models need to span length scales of nearly eight orders of magnitude and require multiphysics analysis, which will be significant challenges. Since increases in CPU and GPU power result in routing losses that have a significant impact on overall system efficiency, integrated voltage regulators are required to supply power at higher voltages. Increased power dissipation will require co-design of system thermal strategies through package thermal design. This situation will be exacerbated in 3D stacked architectures, which will create cumulative effective power densities that require careful inter-stack layout optimization to reduce the power density that the architecture needs to support.
The extreme interconnect density requirements of next-generation packaging will drive the development of ultra-fine pitch (pitch less than 10 μm) and ultra-fine line/space (less than 1 μm L/S) circuits. Assembly technologies and processes require a transition from solder-based interconnects to solderless interconnects (copper-to-copper). This transition will require the development of silicon stacking solutions and tools for chip-to-chip or chip-to-chip hybrid bonding. Finally, the need for smaller size, lighter weight and lower cost will drive reliability and testing challenges. While certification metrics may not change significantly in the next 10 years, achieving the same reliability metrics will be challenging if these new materials, new processes and new dimensions are not designed with reliability considerations in mind.
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