Foreword:

In January this year, the Dutch company ASML successfully developed the first High-NA EUV lithography machine and conducted its first unboxing display in front of the public.

Its innovative technology can further reduce the world's most cutting-edge chip manufacturing process from 3 nanometers to 2 nanometers, bringing an epoch-making breakthrough to the global semiconductor industry.

The debut of this achievement marks that semiconductor manufacturers have officially opened a new era of mass production of 2-nanometer chips.

01 2nm chip technology reserves continue to improve

At present, the technical reserves of the entire semiconductor industry chain are being gradually optimized. From equipment manufacturers to material suppliers to chip design companies, all links are actively responding to technological changes to ensure that they remain competitive in the 2-nanometer chip era.

Previously, the industry generally believed that silicon-based chips would come to an end in the 2-nanometer era, and more advanced chips would use photonic or carbon-based technologies.

However, the emergence of high numerical aperture technology is expected to extend the service life of EUV (extreme ultraviolet lithography) light source technology and alleviate the urgent need for etching light wavelengths.

ASML, the world's largest lithography machine manufacturer, has delivered the latest generation [0.55 numerical aperture] EUV lithography tools to Intel Corporation of the United States, which will provide strong support for the production of 2-nanometer process chips.

According to the "Nihon Keizai Shimbun" report, Canon is working on developing an innovative nanoimprint technology that has huge potential to produce 2-nanometer-level semiconductors.

Therefore, this technology is expected to realize the production of chips with 2nm process and above based on existing light source technology.

In addition, backside power supply (BSPDN) technology, which is regarded as the core technology of the 2nm chip process, has also made significant progress.

The BSPDN technology being developed by Samsung Electronics has achieved new breakthroughs and is planned to be applied in the 2nm chip process in 2025 in advance.

Intel has also invested heavily in the research and development of backside power supply technology in order to restore its leading position in process technology.

The company plans to combine PowerVia with RibbonFET (omnidirectional gate) transistors at the 20A node (2nm), which is expected to achieve 6% performance improvement (Fmax), 90% cell utilization and 30%+ by adopting BPD The voltage drop is reduced.

TSMC has developed a backside power rail solution in N2. This design is particularly suitable for high-performance computing (HPC) applications.

Compared with baseline technology, the backside circuit is expected to increase speed by 10% to 12%, while also increasing logic density by 10% to 15%.

In terms of transistor architecture, according to supply chain news, TSMC plans to use GAA (all gate surround) technology to produce 2-nanometer process nodes.

The Baoshan P1 wafer fab located in the Hsinchu Science Park will start installing equipment as early as April, while the P2 factory and the Kaohsiung factory plan to start producing 2-nanometer process chips using GAA technology in 2025.

02 TSMC: Stable development brought about by long-term leadership

TSMC has long been the world's leader in wafer foundry. Its investment in advanced process technology and R&D capabilities give it an advantage in the industry.

TSMC has announced that it will launch a 2-nanometer process technology in 2025, named N2. This technology will use GAAFET all-around gate transistor technology, and it is expected that performance and efficiency will be significantly improved.

TSMC's advantage lies in its robust technology development strategy and deep accumulation of process technology.

It tends to ensure that new technologies are mature and reliable before deployment. This approach helps reduce the risk of technology failure, improves chip yield and quality, and ensures customer satisfaction.

TSMC has a wide range of customer base, including Apple, Nvidia, AMD, etc. These cooperative relationships provide it with a stable source of orders and revenue, which is helpful for its research and development and mass production of 2-nanometer technology.

As a leader in the global wafer foundry field, TSMC has demonstrated outstanding strength in technology research and development and production capacity layout.

Currently, the Fab20 P1 factory located in Baoshan, Hsinchu, will start the equipment installation project in April to fully prepare for the upcoming mass production of 2-nanometer chips.

TSMC has made it clear that its three advanced process fabs, including Baoshan P1, P2 and Kaohsiung, plan to achieve mass production goals in 2025.

This move has attracted widespread attention from global technology giants. Companies such as Apple, Nvidia, AMD and Qualcomm are actively seeking cooperation with TSMC to ensure sufficient production capacity support.

According to previous wccftech media reports, Apple's iPhone, Mac, iPad and other related devices will become the first users of TSMC's 2nm process technology.

Apple plans to use TSMC's 2nm process technology to improve the performance of its chips and reduce power consumption. This technological innovation is expected to extend the battery life of Apple products such as iPhones and MacBooks in the future.

In terms of 2nm chip production capacity layout, TSMC is currently actively building two 2nm chip factories.

03 Samsung: It will have more experience in the new structure

Samsung Electronics is one of the world's leading semiconductor manufacturers, and its foundry department has also shown strong competitiveness in the research and development of 2-nanometer technology.

Samsung has received many 2nm AI accelerator orders, including orders from Japanese AI giant Preferred Networks Inc. (PFN), which shows Samsung's determination and progress in commercializing 2nm technology.

Samsung’s 2nm-level SF2 process is scheduled to be launched in 2025 and is expected to provide significant improvements in power efficiency and performance.

Samsung's advantage lies in its vertically integrated business model, which has both chip design and manufacturing capabilities, which allows Samsung to coordinate design and production internally and respond quickly to market changes.

In addition, Samsung has adopted the GAA architecture in the 3nm process, which has laid the foundation for its further development in 2nm technology.

Samsung has high hopes for its 2nm node technology. According to relevant reports, compared with the second-generation 3nm GAA design, this node can achieve a 25% efficiency improvement at the same clock frequency.

In addition, the node is expected to be 12% more efficient and reduce the overall chip size by 5% while maintaining the same power level.

Considering that Samsung has made it clear before that its first batch of 2nm wafers will be mainly targeted at the smartphone market, the signing of this new agreement is likely to be the first important contract for Samsung's most advanced process technology in the PC field.

Industry insiders speculate that the target customers of this transaction may be companies with ultra-large data centers such as Google, Microsoft or Alibaba.

However, although Samsung has successfully developed the [second-generation 3nm] process and renamed it [2nm], and plans to officially put it into mass production before the end of this year, the industry does not fully agree with this.

Many major manufacturers are looking forward to the arrival of real 2nm technology and looking forward to seeing Samsung's further breakthroughs in process technology research and development.

Samsung plans to first achieve mass production of 2nm process chips for mobile terminals in 2025, then apply it to high-performance computing (HPC) products in 2026, and further expand to the field of automotive chips in 2027.

04 Intel: Then block and then seize the market

As a veteran giant in the semiconductor industry, Intel has encountered challenges in the 10-nanometer process, but it has also shown strong counterattack intentions in the research and development of 2-nanometer technology.

Intel announced that it will produce next-generation chips by the end of 2024 and has begun promoting its next-generation Intel18A (equivalent to 1.8 nanometer) process node, indicating that Intel hopes to regain its leading position in the competition with 2-nanometer technology.

Both 18A and N2 adopt GAA transistor (RibbonFET) technology, but the 1.8-nanometer node is expected to use BSPND, the backside power delivery network technology, which helps optimize power and clock performance.

The 20A manufacturing technology is expected to be put into use in 2024, and will introduce two innovative technologies: RibbonFET surround-gate transistor and backside power supply network (BSPDN), aiming to achieve goals such as performance improvement, power consumption reduction and transistor density increase.

At the same time, Intel's 18A production node aims to further consolidate and expand the innovative achievements of 20A technology, and is expected to provide more significant PPA performance improvements from the end of 2024 to early 2025.

According to Intel's process planning, its 2-nanometer technology is expected to be the first to be commercialized.

Intel's advantage lies in its leading position in High-NA EUV lithography machines. The company has ordered up to 6 new-generation high-NA EUV lithography machines, which will provide it with higher throughput and finer exposure dimensions. .

Intel is also advancing the use of backside power supply technology and RibbonFET, which are expected to be used in chips coming out in the first quarter of 2024.

At the recent Direct Connect event, Intel announced its [4-year, 5-process node advancement plan], which explicitly includes the development node of 2nm chips.

The company further emphasized its goal to become the world's second-largest foundry by 2030.

Currently, Intel has announced its plan to mass produce 20A [2nm] chips in 2024.

This chip will use innovative RibbonFET transistor technology to replace the traditional FinFET architecture and introduce new interconnect technologies including PowerVia.

In order to improve the performance of its foundry business, Intel is accelerating the research and development of the 2-nanometer process. At the same time, the company is working to promote the independent development of its foundry business.

Starting in the first quarter of 2024, Intel's financial structure will be divided into two major segments: Intel Foundry and Intel Products.

This move marks Intel Foundry officially becoming an independent operating unit and will have its own profit and loss statement.

05 Qualcomm: The market determines the head of cooperation

Qualcomm, as the world's leading wireless communications technology company, has an important position in the mobile processor market.

Although Qualcomm is primarily a fabless semiconductor company and is not directly involved in chip manufacturing, it has significant influence in selecting foundries.

Qualcomm's flagship products, such as the Snapdragon series, have always been the first choice in the high-end smartphone market.

In the competition for 2nm technology, Qualcomm’s strategy is to choose the best foundry to produce the chips it designs.

Qualcomm may decide on foundry partners for its chips based on the technological progress, cost-effectiveness and supply chain stability of foundries such as TSMC and Samsung.

For example, there are reports that Qualcomm plans to use Samsung's [SF2] chip in its next-generation high-end smartphone application processor, which shows that Qualcomm is not only focusing on technical performance, but also on cost and market competitiveness when evaluating 2-nanometer technology.

2nm process technology has become a new battlefield for the global semiconductor industry. Competition among major manufacturers will promote the rapid development and widespread application of technology, bringing more powerful performance and higher energy efficiency ratio to future electronic products and smart applications.

With the continuous advancement of technology and the continuous expansion of the market, 2-nanometer process technology will undoubtedly become an important milestone in the future semiconductor industry.

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