TSMC founder Morris Chang has commented on the high cost of building a fab in Arizona and higher operating costs in the U.S., which gives the impression that it is too expensive to produce chips in the U.S. to be economically viable. However, analysts at TechInsights argue that this is not the case. According to recent research by the firm, wafers at TSMC's Fab 21 fab near Phoenix, Arizona, cost only about 10% more than similar wafers produced in Taiwan.

"TSMC's cost to process a 300mm wafer in Arizona is less than 10% higher than the same wafer made in Taiwan," wrote G. Dan Hutcheson of TechInsights.

01 While it is certainly more expensive to build a fab in the U.S. than in Taiwan?

TSMC's costs are significantly higher because it is building a fab overseas for the first time in decades, in a brand new location, and with workers who are sometimes unskilled, Hutcheson said. According to other people familiar with the fab construction process, it would not cost twice as much to build a fab in the U.S. as it would in Taiwan.

The main factor in semiconductor production costs is the cost of equipment, which accounts for more than two-thirds of the total cost of a wafer. Tools made by leading companies such as ASML, Applied Materials, KLA, Lam Research, or Tokyo Electron cost the same in Taiwan and the United States; they effectively offset location-based cost differences.

One major reason wafer prices are confusing is labor costs. Wages in the U.S. are about three times higher than in Taiwan, and many people mistakenly assume that this is a significant factor in chip production. However, with advanced automation in today's wafer manufacturing facilities, labor accounts for less than 2% of total costs, according to TechInsights' wafer cost model. According to the model, despite the large differences in wages and other local costs, the overall expense gap between operating costs for wafer fabs in Arizona and Taiwan is small.

It is worth noting that the wafers currently produced by TSMC at Fab 21 are returned to Taiwan for dicing, testing, and packaging. Some of these are then shipped to China or elsewhere for use in actual devices; but some are shipped back to the U.S. Their logistics are therefore a bit more complicated than those of a typical wafer processed in Taiwan. However, this hardly increases costs significantly, and TSMC now plans to build packaging capacity in the U.S. Despite this, TSMC is rumored to charge a 30% premium for chips produced in the U.S.

01 Which TSMC process makes the most money?

By now, most of us know that TSMC has a lot of mature process manufacturing capacity. They continue to operate older fabs even after they move to more advanced nodes.

In 2024, nearly 50% of TSMC's revenue will come from nodes that are five years old or older - 7nm and above. This is in stark contrast to Intel, which shuts down older nodes when it moves to newer processes. When Intel made this decision, it made sense for their business model, but now that they are trying to get into the foundry business, lack of capacity is another obstacle.

However, we were curious about how profitable TSMC's older nodes really are. The company reports revenue by node, but there is little information beyond that. Based on this information and some guesstimates, we did some calculations.

The chart below shows their revenue distribution by node in 2024.

Advanced nodes (3nm and 5nm combined) contributed 52%. In comparison, the chart below shows operating profit by node.

Specifically, TSMC's advanced nodes generate 52% of revenue but only 27% of profits. That being said, it's important to remember that nodes (especially 3nm) are still in very early stages and profitability is improving rapidly.

The 2023 data actually shows both 3nm and 5nm losing money. They have made a lot of progress in recent years, and we estimate that by next year, revenue share and profit share will be much closer. Just in time for the launch of the new nodes.

02 Methodological Notes

We realize that not everyone enjoys the complexity of building models as much as we do. So we saved this section for the end, for those who can understand.

TSMC only breaks out revenue by node, not profitability or expenses, but it's enough to get started.

The main driver of this model is depreciation. The key to TSMC's financials is that older nodes are fully depreciated. The company depreciates its equipment over five years. So 7nm, introduced in 2017, is the depreciation dividing line. All newer nodes (3nm and 5nm) are still subject to depreciation burdens.

More than 90% of the company's depreciation expense is included in cost of goods sold (COGS). So for our purposes, we allocated depreciation to the two advanced nodes based on their revenue share. Then, we allocated the remaining COGS (minus depreciation) across all nodes based on revenue share. This may be a bit biased - older wafers may cost less and require fewer steps - but our sense is that the difference is small.

Then we looked at R&D. We assume that most of the R&D expenses are for the latest nodes, and again allocate expenses to the 3nm and 5nm nodes. This is actually a bit inaccurate because our assumption is that most of the R&D expenses are for nodes that are not yet in production.

However, we believe that both advanced nodes still require considerable R&D costs to move up the learning curve and increase yields (especially 3nm). Therefore, this overestimates costs to a certain extent, but it is a level we are comfortable with.

Finally, we allocate SG&A expenses equally to each node based on the revenue share of each node. This may overstate the costs of older nodes, because these nodes may not require as much management time or sales resources. We realize that not everyone likes the complexity of building models as much as we do. So we save this part for the end, for those who can understand.

TSMC only reports revenue by node, not profitability or expenses, but it is enough to get started.

The main driver of this model is depreciation. The key to TSMC's financials is that older nodes are fully depreciated. The company depreciates its equipment over a five-year period. So, 7nm, introduced in 2017, is the depreciation dividing line. All newer nodes (3nm and 5nm) still have to bear the burden of depreciation.

More than 90% of the company's depreciation expense is recorded in cost of goods sold (COGS). So for our purposes, we allocated depreciation to the two advanced nodes based on their revenue share. Then, we allocated the remaining COGS (minus depreciation) across all nodes based on revenue share. This may be a bit biased - older wafers may cost less and require fewer steps - but our sense is that the difference is small.

Then we looked at R&D. We assumed that most of the R&D expenses were spent on the latest nodes and again allocated the expenses to the 3nm and 5nm nodes. This is actually a bit inaccurate because our assumption is that most of the R&D expenses are spent on nodes that are not yet in production.

However, we believe that both advanced nodes still require considerable R&D costs to get up the learning curve and increase production (especially 3nm). So this is a bit of an overestimation of costs, but it is a level we are comfortable with.

Finally, we allocated SG&A expenses equally to each node based on their share of revenue. This may overstate the costs of older nodes, which may not require as much management time or sales resources.

Reference link: https://www.tomshardware.com/tech-industry/producing-wafers-at-tsmc-arizona-is-only-10-percent-more-expensive-than-in-taiwan-techinsights

Source: Content from techinsights, etc.

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